Timing Messages

Report Title	Timing Analysis Report
Design File	D:\Projects\GOWIN\DF2\DF2\impl\gwsynthesis\DF2.vg
Physical Constraints File	---
Timing Constraint File	---
Version	V1.9.8.09
Part Number	GW1N-LV4LQ144C6/I5
Device	GW1N-4
Created Time	Sat Jan 20 17:56:34 2024
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	3252
Numbers of Endpoints Analyzed	2675
Numbers of Falling Endpoints	8
Numbers of Setup Violated Endpoints	36
Numbers of Hold Violated Endpoints	37

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
iCLK	Base	20.000	50.000	0.000	10.000			iCLK_ibuf/I
iSCK	Base	20.000	50.000	0.000	10.000			iSCK_ibuf/I
iSPI_SCK	Base	20.000	50.000	0.000	10.000			iSPI_SCK_ibuf/I
_SAI_INPUT/rLRC	Base	20.000	50.000	0.000	10.000			_SAI_INPUT/rLRC_s0/Q
_DF2_FIR_CORE/_DF_CONTROL/n820_5	Base	20.000	50.000	0.000	10.000			_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
iDF_MODE_d[1]	Base	20.000	50.000	0.000	10.000			iDF_MODE_1_ibuf/O

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	iCLK	50.000(MHz)	39.135(MHz)	18	TOP
2	iSCK	50.000(MHz)	218.472(MHz)	3	TOP
3	iSPI_SCK	50.000(MHz)	124.154(MHz)	5	TOP
4	iDF_MODE_d[1]	50.000(MHz)	261.336(MHz)	2	TOP

No timing paths to get frequency of _SAI_INPUT/rLRC!

No timing paths to get frequency of _DF2_FIR_CORE/_DF_CONTROL/n820_5!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
iCLK	Setup	-73.232	36
iCLK	Hold	0.000	0
iSCK	Setup	0.000	0
iSCK	Hold	0.000	0
iSPI_SCK	Setup	0.000	0
iSPI_SCK	Hold	0.000	0
_SAI_INPUT/rLRC	Setup	0.000	0
_SAI_INPUT/rLRC	Hold	0.000	0
_DF2_FIR_CORE/_DF_CONTROL/n820_5	Setup	0.000	0
_DF2_FIR_CORE/_DF_CONTROL/n820_5	Hold	0.000	0
iDF_MODE_d[1]	Setup	0.000	0
iDF_MODE_d[1]	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-5.552	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_23_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	25.152
2	-5.495	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_22_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	25.095
3	-5.083	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_21_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	24.683
4	-4.206	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_20_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	23.806
5	-3.794	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_19_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	23.394
6	-3.589	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_23_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	23.189
7	-3.362	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_22_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	22.962
8	-2.950	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_21_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	22.550
9	-2.644	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_15_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	22.244
10	-2.620	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_13_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	22.220
11	-2.566	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_18_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	22.166
12	-2.249	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rSUML_23_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.849
13	-2.215	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_20_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.815
14	-2.208	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rSUML_22_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.808
15	-2.135	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rSUML_21_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.735
16	-2.078	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rSUML_20_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.678
17	-2.073	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_12_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.673
18	-1.995	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_17_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.595
19	-1.938	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_16_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.538
20	-1.911	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_14_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.511
21	-1.803	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_19_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.403
22	-1.649	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQL_11_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.249
23	-1.502	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_14_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	21.102
24	-1.176	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q	_DF2_FIR_CORE/_DATA_READ/rSUML_19_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	20.776
25	-1.066	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q	_DF2_FIR_CORE/_DATA_READ/rQR_18_s0/D	iCLK:[R]	iCLK:[R]	20.000	0.000	20.666

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.534	_DF2_FIR_CORE/_DF_CONTROL/n865_s0/I2	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/D	iDF_MODE_d[1]:[F]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	0.000	-1.680	1.176
2	-0.534	_DF2_FIR_CORE/_DF_CONTROL/n819_s0/I3	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/D	iDF_MODE_d[1]:[F]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	0.000	-1.680	1.176
3	-0.400	_SAI_INPUT/rSHH_15_s0/Q	_SAI_INPUT/rDL_14_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.309	0.940
4	-0.397	_SAI_INPUT/rSHL_10_s0/Q	_SAI_INPUT/rDR_9_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.937
5	-0.397	_SAI_INPUT/rSHH_26_s0/Q	_SAI_INPUT/rDL_26_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.937
6	-0.393	_SAI_INPUT/rSHL_19_s0/Q	_SAI_INPUT/rDR_18_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.940
7	-0.393	_SAI_INPUT/rSHL_24_s0/Q	_SAI_INPUT/rDR_23_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.940
8	-0.393	_SAI_INPUT/rSHH_24_s0/Q	_SAI_INPUT/rDL_23_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.940
9	-0.390	_SAI_INPUT/rSHL_26_s0/Q	_SAI_INPUT/rDR_26_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.937
10	-0.387	_SAI_INPUT/rSHL_6_s0/Q	_SAI_INPUT/rDR_5_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.940
11	-0.387	_SAI_INPUT/rSHH_6_s0/Q	_SAI_INPUT/rDL_5_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.940
12	-0.387	_SAI_INPUT/rSHH_22_s0/Q	_SAI_INPUT/rDL_21_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.940
13	-0.383	_SAI_INPUT/rSHH_18_s0/Q	_SAI_INPUT/rDL_17_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.944
14	-0.372	_SAI_INPUT/rSHH_23_s0/Q	_SAI_INPUT/rDL_22_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.961
15	-0.366	_SAI_INPUT/rSHL_25_s0/Q	_SAI_INPUT/rDR_24_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	0.961
16	-0.349	_SAI_INPUT/rSHL_8_s0/Q	_SAI_INPUT/rDR_7_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	0.984
17	-0.120	_SAI_INPUT/rSHH_13_s0/Q	_SAI_INPUT/rDL_12_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.309	1.220
18	-0.114	_SAI_INPUT/rSHL_23_s0/Q	_SAI_INPUT/rDR_22_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	1.220
19	-0.108	_SAI_INPUT/rSHH_10_s0/Q	_SAI_INPUT/rDL_9_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	1.218
20	-0.107	_SAI_INPUT/rSHL_5_s0/Q	_SAI_INPUT/rDR_4_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	1.220
21	-0.079	_SAI_INPUT/rSHH_11_s0/Q	_SAI_INPUT/rDL_10_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	1.248
22	-0.066	_SAI_INPUT/rSHL_15_s0/Q	_SAI_INPUT/rDR_14_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	1.267
23	-0.066	_SAI_INPUT/rSHL_17_s0/Q	_SAI_INPUT/rDR_16_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.303	1.267
24	-0.060	_SAI_INPUT/rSHL_22_s0/Q	_SAI_INPUT/rDR_21_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.297	1.267
25	-0.051	_SAI_INPUT/rSHH_4_s0/Q	_SAI_INPUT/rDL_3_s0/D	iSCK:[R]	_SAI_INPUT/rLRC:[R]	0.000	-1.309	1.289

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.207	_SAI_INPUT/rCntH_0_s1/CLEAR	_SAI_INPUT/rCntH_0_s1/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
2	8.207	_SAI_INPUT/rCntL_0_s1/CLEAR	_SAI_INPUT/rCntL_0_s1/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
3	8.207	_SAI_INPUT/rCntL_4_s0/CLEAR	_SAI_INPUT/rCntL_4_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
4	8.207	_SAI_INPUT/rCntH_1_s0/CLEAR	_SAI_INPUT/rCntH_1_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
5	8.207	_SAI_INPUT/rCntH_2_s0/CLEAR	_SAI_INPUT/rCntH_2_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
6	8.207	_SAI_INPUT/rCntH_3_s0/CLEAR	_SAI_INPUT/rCntH_3_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
7	8.207	_SAI_INPUT/rCntH_4_s0/CLEAR	_SAI_INPUT/rCntH_4_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
8	8.207	_SAI_INPUT/rCntL_1_s0/CLEAR	_SAI_INPUT/rCntL_1_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
9	8.207	_SAI_INPUT/rCntL_2_s0/CLEAR	_SAI_INPUT/rCntL_2_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
10	8.207	_SAI_INPUT/rCntL_3_s0/CLEAR	_SAI_INPUT/rCntL_3_s0/CLEAR	_SAI_INPUT/rLRC:[F]	iSCK:[R]	10.000	-1.226	2.946
11	10.653	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/PRESET	iDF_MODE_d[1]:[R]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	10.000	-2.365	1.639
12	10.653	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/CLEAR	iDF_MODE_d[1]:[R]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	10.000	-2.365	1.639
13	19.158	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR	iDF_MODE_d[1]:[F]	iDF_MODE_d[1]:[F]	20.000	-0.262	1.061
14	19.158	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR	iDF_MODE_d[1]:[F]	iDF_MODE_d[1]:[F]	20.000	-0.262	1.061

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.652	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/PRESET	iDF_MODE_d[1]:[F]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	0.000	-1.680	1.073
2	-0.652	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/CLEAR	iDF_MODE_d[1]:[F]	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]	0.000	-1.680	1.073
3	0.753	_SAI_INPUT/rCntH_0_s1/CLEAR	_SAI_INPUT/rCntH_0_s1/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
4	0.753	_SAI_INPUT/rCntL_0_s1/CLEAR	_SAI_INPUT/rCntL_0_s1/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
5	0.753	_SAI_INPUT/rCntL_4_s0/CLEAR	_SAI_INPUT/rCntL_4_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
6	0.753	_SAI_INPUT/rCntH_1_s0/CLEAR	_SAI_INPUT/rCntH_1_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
7	0.753	_SAI_INPUT/rCntH_2_s0/CLEAR	_SAI_INPUT/rCntH_2_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
8	0.753	_SAI_INPUT/rCntH_3_s0/CLEAR	_SAI_INPUT/rCntH_3_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
9	0.753	_SAI_INPUT/rCntH_4_s0/CLEAR	_SAI_INPUT/rCntH_4_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
10	0.753	_SAI_INPUT/rCntL_1_s0/CLEAR	_SAI_INPUT/rCntL_1_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
11	0.753	_SAI_INPUT/rCntL_2_s0/CLEAR	_SAI_INPUT/rCntL_2_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
12	0.753	_SAI_INPUT/rCntL_3_s0/CLEAR	_SAI_INPUT/rCntL_3_s0/CLEAR	_SAI_INPUT/rLRC:[R]	iSCK:[R]	0.000	-1.029	1.827
13	10.543	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR	iDF_MODE_d[1]:[R]	iDF_MODE_d[1]:[F]	-10.000	-0.195	0.754
14	10.543	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR	iDF_MODE_d[1]:[R]	iDF_MODE_d[1]:[F]	-10.000	-0.195	0.754

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_14_s0
2	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_12_s0
3	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_3_s0
4	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_1_s0
5	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_0_s0
6	7.308	8.558	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDL_8_s0
7	7.311	8.561	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDR_0_s0
8	7.311	8.561	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDR_16_s0
9	7.311	8.561	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDR_8_s0
10	7.311	8.561	1.250	Low Pulse Width	_SAI_INPUT/rLRC	_SAI_INPUT/rDR_7_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-5.552
Data Arrival Time	26.378
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_23_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
21.468	0.563	tINS	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/SUM
22.779	1.311	tNET	FF	2	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/I0
23.824	1.045	tINS	FF	1	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/COUT
23.824	0.000	tNET	FF	2	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/CIN
24.387	0.563	tINS	FF	1	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/SUM
25.208	0.821	tNET	FF	2	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/I1
25.758	0.550	tINS	FR	1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/COUT
25.758	0.000	tNET	RR	2	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/CIN
25.815	0.057	tINS	RF	1	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/COUT
25.815	0.000	tNET	FF	2	R8C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_23_s0/CIN
26.378	0.563	tINS	FF	1	R8C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_23_s0/SUM
26.378	0.000	tNET	FF	1	R8C26[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C26[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_23_s0/CLK
20.826	-0.400	tSu		1	R8C26[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	18
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 14.724, 58.539%; route: 9.970, 39.638%; tC2Q: 0.458, 1.822%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path2

Path Summary:

Slack	-5.495
Data Arrival Time	26.321
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_22_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
21.468	0.563	tINS	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/SUM
22.779	1.311	tNET	FF	2	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/I0
23.824	1.045	tINS	FF	1	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/COUT
23.824	0.000	tNET	FF	2	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/CIN
24.387	0.563	tINS	FF	1	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/SUM
25.208	0.821	tNET	FF	2	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/I1
25.758	0.550	tINS	FR	1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/COUT
25.758	0.000	tNET	RR	2	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/CIN
26.321	0.563	tINS	RF	1	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/SUM
26.321	0.000	tNET	FF	1	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_22_s0/CLK
20.826	-0.400	tSu		1	R8C26[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	18
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 14.667, 58.445%; route: 9.970, 39.728%; tC2Q: 0.458, 1.826%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path3

Path Summary:

Slack	-5.083
Data Arrival Time	25.909
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_21_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
21.468	0.563	tINS	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/SUM
22.779	1.311	tNET	FF	2	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/I0
23.824	1.045	tINS	FF	1	R9C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/COUT
23.824	0.000	tNET	FF	2	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/CIN
24.387	0.563	tINS	FF	1	R9C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/SUM
25.208	0.821	tNET	FF	2	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/I1
25.909	0.701	tINS	FR	1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/SUM
25.909	0.000	tNET	RR	1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_21_s0/CLK
20.826	-0.400	tSu		1	R8C26[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	17
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 14.255, 57.752%; route: 9.970, 40.392%; tC2Q: 0.458, 1.857%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path4

Path Summary:

Slack	-4.206
Data Arrival Time	25.032
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_20_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.921	1.032	tINS	FF	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.426	0.506	tNET	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/I1
17.458	1.032	tINS	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/F
18.263	0.804	tNET	FF	2	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/I0
19.308	1.045	tINS	FF	1	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/COUT
19.308	0.000	tNET	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/CIN
19.871	0.563	tINS	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/SUM
21.176	1.305	tNET	FF	2	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/I0
22.221	1.045	tINS	FF	1	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/COUT
22.221	0.000	tNET	FF	2	R9C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s/CIN
22.784	0.563	tINS	FF	1	R9C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s/SUM
23.919	1.135	tNET	FF	2	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s0/I1
24.469	0.550	tINS	FR	1	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s0/COUT
24.469	0.000	tNET	RR	2	R8C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s0/CIN
25.032	0.563	tINS	RF	1	R8C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_20_s0/SUM
25.032	0.000	tNET	FF	1	R8C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_20_s0/CLK
20.826	-0.400	tSu		1	R8C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	17
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 13.641, 57.300%; route: 9.707, 40.775%; tC2Q: 0.458, 1.925%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path5

Path Summary:

Slack	-3.794
Data Arrival Time	24.620
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_19_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.921	1.032	tINS	FF	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.426	0.506	tNET	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/I1
17.458	1.032	tINS	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/F
18.263	0.804	tNET	FF	2	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/I0
19.308	1.045	tINS	FF	1	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/COUT
19.308	0.000	tNET	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/CIN
19.871	0.563	tINS	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/SUM
21.176	1.305	tNET	FF	2	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/I0
22.221	1.045	tINS	FF	1	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/COUT
22.221	0.000	tNET	FF	2	R9C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s/CIN
22.784	0.563	tINS	FF	1	R9C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s/SUM
23.919	1.135	tNET	FF	2	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s0/I1
24.620	0.701	tINS	FR	1	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_19_s0/SUM
24.620	0.000	tNET	RR	1	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rQL_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rQL_19_s0/CLK
20.826	-0.400	tSu		1	R8C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rQL_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 13.229, 56.548%; route: 9.707, 41.493%; tC2Q: 0.458, 1.959%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path6

Path Summary:

Slack	-3.589
Data Arrival Time	24.415
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_23_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.351	0.814	tNET	FF	1	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.977	0.626	tINS	FF	4	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.999	0.022	tNET	FF	1	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.625	0.626	tINS	FF	4	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.441	0.815	tNET	FF	1	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/I3
7.473	1.032	tINS	FF	9	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.511	0.038	tNET	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.610	1.099	tINS	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/F
9.414	0.804	tNET	FF	2	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.964	0.550	tINS	FR	1	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.964	0.000	tNET	RR	2	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/CIN
10.021	0.057	tINS	RF	1	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/COUT
10.021	0.000	tNET	FF	2	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/CIN
10.584	0.563	tINS	FF	4	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/SUM
11.895	1.311	tNET	FF	1	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I0
12.921	1.026	tINS	FR	3	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
13.344	0.423	tNET	RR	1	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.970	0.626	tINS	RF	4	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
14.803	0.832	tNET	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
15.902	1.099	tINS	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.907	0.005	tNET	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.939	1.032	tINS	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
18.228	1.289	tNET	FF	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
19.273	1.045	tINS	FF	1	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
19.273	0.000	tNET	FF	2	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
19.330	0.057	tINS	FF	1	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/COUT
19.330	0.000	tNET	FF	2	R16C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_21_s/CIN
19.893	0.563	tINS	FF	2	R16C26[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_21_s/SUM
20.873	0.980	tNET	FF	2	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/I0
21.918	1.045	tINS	FF	1	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/COUT
21.918	0.000	tNET	FF	2	R15C25[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s/CIN
22.481	0.563	tINS	FF	1	R15C25[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s/SUM
23.302	0.821	tNET	FF	2	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/I1
23.852	0.550	tINS	FR	1	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/COUT
23.852	0.000	tNET	RR	2	R14C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_23_s0/CIN
24.415	0.563	tINS	RF	1	R14C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_23_s0/SUM
24.415	0.000	tNET	FF	1	R14C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQR_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQR_23_s0/CLK
20.826	-0.400	tSu		1	R14C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQR_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	18
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 13.754, 59.312%; route: 8.977, 38.711%; tC2Q: 0.458, 1.976%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path7

Path Summary:

Slack	-3.362
Data Arrival Time	24.188
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_22_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.351	0.814	tNET	FF	1	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.977	0.626	tINS	FF	4	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.999	0.022	tNET	FF	1	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.625	0.626	tINS	FF	4	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.441	0.815	tNET	FF	1	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/I3
7.473	1.032	tINS	FF	9	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.511	0.038	tNET	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.610	1.099	tINS	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/F
9.414	0.804	tNET	FF	2	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.964	0.550	tINS	FR	1	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.964	0.000	tNET	RR	2	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/CIN
10.021	0.057	tINS	RF	1	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/COUT
10.021	0.000	tNET	FF	2	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/CIN
10.584	0.563	tINS	FF	4	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/SUM
11.895	1.311	tNET	FF	1	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I0
12.921	1.026	tINS	FR	3	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
13.344	0.423	tNET	RR	1	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.970	0.626	tINS	RF	4	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
14.803	0.832	tNET	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
15.902	1.099	tINS	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.907	0.005	tNET	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.939	1.032	tINS	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
18.228	1.289	tNET	FF	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
19.273	1.045	tINS	FF	1	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
19.273	0.000	tNET	FF	2	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
19.836	0.563	tINS	FF	2	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/SUM
20.646	0.810	tNET	FF	2	R15C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/I0
21.691	1.045	tINS	FF	1	R15C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/COUT
21.691	0.000	tNET	FF	2	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/CIN
22.254	0.563	tINS	FF	1	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/SUM
23.075	0.821	tNET	FF	2	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/I1
23.625	0.550	tINS	FR	1	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/COUT
23.625	0.000	tNET	RR	2	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/CIN
24.188	0.563	tINS	RF	1	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/SUM
24.188	0.000	tNET	FF	1	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQR_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQR_22_s0/CLK
20.826	-0.400	tSu		1	R14C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQR_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	18
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 13.697, 59.651%; route: 8.807, 38.353%; tC2Q: 0.458, 1.996%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path8

Path Summary:

Slack	-2.950
Data Arrival Time	23.776
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_21_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.351	0.814	tNET	FF	1	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.977	0.626	tINS	FF	4	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.999	0.022	tNET	FF	1	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.625	0.626	tINS	FF	4	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.441	0.815	tNET	FF	1	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/I3
7.473	1.032	tINS	FF	9	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.511	0.038	tNET	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.610	1.099	tINS	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/F
9.414	0.804	tNET	FF	2	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.964	0.550	tINS	FR	1	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.964	0.000	tNET	RR	2	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/CIN
10.021	0.057	tINS	RF	1	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/COUT
10.021	0.000	tNET	FF	2	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/CIN
10.584	0.563	tINS	FF	4	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/SUM
11.895	1.311	tNET	FF	1	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I0
12.921	1.026	tINS	FR	3	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
13.344	0.423	tNET	RR	1	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.970	0.626	tINS	RF	4	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
14.803	0.832	tNET	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
15.902	1.099	tINS	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.907	0.005	tNET	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.939	1.032	tINS	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
18.228	1.289	tNET	FF	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
19.273	1.045	tINS	FF	1	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
19.273	0.000	tNET	FF	2	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
19.836	0.563	tINS	FF	2	R16C26[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/SUM
20.646	0.810	tNET	FF	2	R15C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/I0
21.691	1.045	tINS	FF	1	R15C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/COUT
21.691	0.000	tNET	FF	2	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/CIN
22.254	0.563	tINS	FF	1	R15C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/SUM
23.075	0.821	tNET	FF	2	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/I1
23.776	0.701	tINS	FR	1	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/SUM
23.776	0.000	tNET	RR	1	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQR_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQR_21_s0/CLK
20.826	-0.400	tSu		1	R14C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQR_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	17
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 13.285, 58.914%; route: 8.807, 39.054%; tC2Q: 0.458, 2.033%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path9

Path Summary:

Slack	-2.644
Data Arrival Time	23.470
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_15_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/I1
9.683	1.026	tINS	FR	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/F
10.102	0.419	tNET	RR	2	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/I1
10.641	0.539	tINS	RF	3	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/SUM
12.105	1.464	tNET	FF	1	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/I1
12.927	0.822	tINS	FF	12	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/F
13.783	0.857	tNET	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/I1
14.882	1.099	tINS	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/F
16.188	1.305	tNET	FF	2	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/I0
17.233	1.045	tINS	FF	1	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/COUT
17.233	0.000	tNET	FF	2	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/CIN
17.796	0.563	tINS	FF	2	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/SUM
18.776	0.980	tNET	FF	2	R9C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s/I0
19.821	1.045	tINS	FF	1	R9C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s/COUT
19.821	0.000	tNET	FF	2	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/CIN
20.384	0.563	tINS	FF	1	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/SUM
20.874	0.490	tNET	FF	2	R8C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s0/I1
21.424	0.550	tINS	FR	1	R8C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s0/COUT
21.424	0.000	tNET	RR	2	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/CIN
21.952	0.528	tINS	RR	1	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/SUM
22.371	0.419	tNET	RR	1	R7C25[0][A]	_DF2_FIR_CORE/_DATA_READ/n1435_s1/I2
23.470	1.099	tINS	RF	1	R7C25[0][A]	_DF2_FIR_CORE/_DATA_READ/n1435_s1/F
23.470	0.000	tNET	FF	1	R7C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_15_s0/CLK
20.826	-0.400	tSu		1	R7C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.826, 57.660%; route: 8.960, 40.279%; tC2Q: 0.458, 2.060%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path10

Path Summary:

Slack	-2.620
Data Arrival Time	23.446
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_13_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
4.426	0.011	tNET	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/I1
5.458	1.032	tINS	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/F
6.262	0.804	tNET	FF	2	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/I1
6.812	0.550	tINS	FR	1	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/COUT
6.812	0.000	tNET	RR	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/CIN
7.375	0.563	tINS	RF	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/SUM
9.005	1.630	tNET	FF	1	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/I2
9.827	0.822	tINS	FF	4	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/F
10.323	0.496	tNET	FF	1	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/I3
11.422	1.099	tINS	FF	4	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/F
12.231	0.810	tNET	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/I1
13.330	1.099	tINS	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/F
14.950	1.620	tNET	FF	2	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/I0
15.995	1.045	tINS	FF	1	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/COUT
15.995	0.000	tNET	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/CIN
16.558	0.563	tINS	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/SUM
17.869	1.311	tNET	FF	2	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/I0
18.914	1.045	tINS	FF	1	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/COUT
18.914	0.000	tNET	FF	2	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/CIN
19.442	0.528	tINS	FR	1	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/SUM
19.861	0.419	tNET	RR	2	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/I0
20.906	1.045	tINS	RF	1	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/COUT
20.906	0.000	tNET	FF	2	R8C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s0/CIN
20.963	0.057	tINS	FF	1	R8C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s0/COUT
20.963	0.000	tNET	FF	2	R8C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s0/CIN
21.526	0.563	tINS	FF	1	R8C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s0/SUM
22.347	0.821	tNET	FF	1	R8C22[0][A]	_DF2_FIR_CORE/_DATA_READ/n1433_s1/I2
23.446	1.099	tINS	FF	1	R8C22[0][A]	_DF2_FIR_CORE/_DATA_READ/n1433_s1/F
23.446	0.000	tNET	FF	1	R8C22[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C22[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_13_s0/CLK
20.826	-0.400	tSu		1	R8C22[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.993, 58.475%; route: 8.769, 39.463%; tC2Q: 0.458, 2.063%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path11

Path Summary:

Slack	-2.566
Data Arrival Time	23.391
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_18_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.921	1.032	tINS	FF	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.426	0.506	tNET	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/I1
17.458	1.032	tINS	FF	1	R9C22[0][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s3/F
18.263	0.804	tNET	FF	2	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/I0
19.308	1.045	tINS	FF	1	R7C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_17_s/COUT
19.308	0.000	tNET	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/CIN
19.871	0.563	tINS	FF	2	R7C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_18_s/SUM
21.176	1.305	tNET	FF	2	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/I0
21.904	0.728	tINS	FR	1	R9C26[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s/SUM
22.690	0.786	tNET	RR	2	R8C25[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s0/I1
23.391	0.701	tINS	RR	1	R8C25[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_18_s0/SUM
23.391	0.000	tNET	RR	1	R8C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rQL_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rQL_18_s0/CLK
20.826	-0.400	tSu		1	R8C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rQL_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.349, 55.712%; route: 9.358, 42.220%; tC2Q: 0.458, 2.068%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path12

Path Summary:

Slack	-2.249
Data Arrival Time	23.075
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rSUML_23_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
20.962	0.057	tINS	FF	1	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/COUT
20.962	0.000	tNET	FF	2	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/CIN
21.019	0.057	tINS	FF	1	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/COUT
21.019	0.000	tNET	FF	2	R7C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_22_s/CIN
21.076	0.057	tINS	FF	1	R7C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_22_s/COUT
21.076	0.000	tNET	FF	2	R7C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_23_s/CIN
21.639	0.563	tINS	FF	2	R7C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_23_s/SUM
23.075	1.436	tNET	FF	1	R6C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R6C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_23_s0/CLK
20.826	-0.400	tSu		1	R6C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.117, 55.457%; route: 9.274, 42.445%; tC2Q: 0.458, 2.098%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path13

Path Summary:

Slack	-2.215
Data Arrival Time	23.041
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_20_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.351	0.814	tNET	FF	1	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.977	0.626	tINS	FF	4	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.999	0.022	tNET	FF	1	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.625	0.626	tINS	FF	4	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.441	0.815	tNET	FF	1	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/I3
7.473	1.032	tINS	FF	9	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.511	0.038	tNET	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.610	1.099	tINS	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/F
9.414	0.804	tNET	FF	2	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.964	0.550	tINS	FR	1	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.964	0.000	tNET	RR	2	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/CIN
10.021	0.057	tINS	RF	1	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/COUT
10.021	0.000	tNET	FF	2	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/CIN
10.584	0.563	tINS	FF	4	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/SUM
11.895	1.311	tNET	FF	1	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I0
12.921	1.026	tINS	FR	3	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
13.344	0.423	tNET	RR	1	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.970	0.626	tINS	RF	4	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
14.803	0.832	tNET	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
15.902	1.099	tINS	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.907	0.005	tNET	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.939	1.032	tINS	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
18.228	1.289	tNET	FF	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
18.956	0.728	tINS	FR	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/SUM
20.079	1.123	tNET	RR	2	R15C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s/I0
20.807	0.728	tINS	RR	1	R15C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s/SUM
21.928	1.121	tNET	RR	2	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s0/I1
22.478	0.550	tINS	RR	1	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s0/COUT
22.478	0.000	tNET	RR	2	R14C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s0/CIN
23.041	0.563	tINS	RF	1	R14C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s0/SUM
23.041	0.000	tNET	FF	1	R14C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQR_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQR_20_s0/CLK
20.826	-0.400	tSu		1	R14C25[0][A]	_DF2_FIR_CORE/_DATA_READ/rQR_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 11.937, 54.720%; route: 9.419, 43.179%; tC2Q: 0.458, 2.101%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path14

Path Summary:

Slack	-2.208
Data Arrival Time	23.034
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rSUML_22_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
20.962	0.057	tINS	FF	1	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/COUT
20.962	0.000	tNET	FF	2	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/CIN
21.019	0.057	tINS	FF	1	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/COUT
21.019	0.000	tNET	FF	2	R7C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_22_s/CIN
21.582	0.563	tINS	FF	2	R7C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_22_s/SUM
23.034	1.451	tNET	FF	1	R7C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_22_s0/CLK
20.826	-0.400	tSu		1	R7C26[0][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.060, 55.301%; route: 9.290, 42.597%; tC2Q: 0.458, 2.102%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path15

Path Summary:

Slack	-2.135
Data Arrival Time	22.961
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rSUML_21_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
20.962	0.057	tINS	FF	1	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/COUT
20.962	0.000	tNET	FF	2	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/CIN
21.525	0.563	tINS	FF	2	R7C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_21_s/SUM
22.961	1.436	tNET	FF	1	R6C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R6C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_21_s0/CLK
20.826	-0.400	tSu		1	R6C25[2][B]	_DF2_FIR_CORE/_DATA_READ/rSUML_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.003, 55.223%; route: 9.274, 42.668%; tC2Q: 0.458, 2.109%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path16

Path Summary:

Slack	-2.078
Data Arrival Time	22.904
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rSUML_20_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.905	1.045	tINS	FF	1	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
20.905	0.000	tNET	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
21.468	0.563	tINS	FF	2	R7C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_20_s/SUM
22.904	1.436	tNET	FF	1	R6C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R6C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_20_s0/CLK
20.826	-0.400	tSu		1	R6C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 11.946, 55.106%; route: 9.274, 42.780%; tC2Q: 0.458, 2.114%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path17

Path Summary:

Slack	-2.073
Data Arrival Time	22.899
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_12_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
4.426	0.011	tNET	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/I1
5.458	1.032	tINS	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/F
6.262	0.804	tNET	FF	2	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/I1
6.812	0.550	tINS	FR	1	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/COUT
6.812	0.000	tNET	RR	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/CIN
7.375	0.563	tINS	RF	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/SUM
9.005	1.630	tNET	FF	1	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/I2
9.827	0.822	tINS	FF	4	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/F
10.323	0.496	tNET	FF	1	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/I3
11.422	1.099	tINS	FF	4	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/F
12.231	0.810	tNET	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/I1
13.330	1.099	tINS	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/F
14.950	1.620	tNET	FF	2	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/I0
15.995	1.045	tINS	FF	1	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/COUT
15.995	0.000	tNET	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/CIN
16.558	0.563	tINS	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/SUM
17.869	1.311	tNET	FF	2	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/I0
18.914	1.045	tINS	FF	1	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/COUT
18.914	0.000	tNET	FF	2	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/CIN
19.442	0.528	tINS	FR	1	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/SUM
19.861	0.419	tNET	RR	2	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/I0
20.906	1.045	tINS	RF	1	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/COUT
20.906	0.000	tNET	FF	2	R8C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s0/CIN
21.469	0.563	tINS	FF	1	R8C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s0/SUM
22.273	0.804	tNET	FF	1	R11C24[0][A]	_DF2_FIR_CORE/_DATA_READ/n1432_s1/I2
22.899	0.626	tINS	FF	1	R11C24[0][A]	_DF2_FIR_CORE/_DATA_READ/n1432_s1/F
22.899	0.000	tNET	FF	1	R11C24[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R11C24[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_12_s0/CLK
20.826	-0.400	tSu		1	R11C24[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.463, 57.504%; route: 8.752, 40.382%; tC2Q: 0.458, 2.115%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path18

Path Summary:

Slack	-1.995
Data Arrival Time	22.821
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_17_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/I1
9.683	1.026	tINS	FR	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/F
10.102	0.419	tNET	RR	2	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/I1
10.641	0.539	tINS	RF	3	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/SUM
12.105	1.464	tNET	FF	1	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/I1
12.927	0.822	tINS	FF	12	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/F
13.783	0.857	tNET	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/I1
14.882	1.099	tINS	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/F
16.188	1.305	tNET	FF	2	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/I0
17.233	1.045	tINS	FF	1	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/COUT
17.233	0.000	tNET	FF	2	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/CIN
17.290	0.057	tINS	FF	1	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/COUT
17.290	0.000	tNET	FF	2	R7C23[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_14_s/CIN
17.853	0.563	tINS	FF	2	R7C23[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_14_s/SUM
19.164	1.311	tNET	FF	2	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/I0
20.209	1.045	tINS	FF	1	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/COUT
20.209	0.000	tNET	FF	2	R9C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s/CIN
20.737	0.528	tINS	FR	1	R9C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s/SUM
21.156	0.419	tNET	RR	2	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/I0
22.201	1.045	tINS	RF	1	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/COUT
22.201	0.000	tNET	FF	2	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_16_s0/CIN
22.258	0.057	tINS	FF	1	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_16_s0/COUT
22.258	0.000	tNET	FF	2	R8C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_17_s0/CIN
22.821	0.563	tINS	FF	1	R8C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_17_s0/SUM
22.821	0.000	tNET	FF	1	R8C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_17_s0/CLK
20.826	-0.400	tSu		1	R8C25[1][B]	_DF2_FIR_CORE/_DATA_READ/rQL_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.336, 57.125%; route: 8.800, 40.753%; tC2Q: 0.458, 2.122%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path19

Path Summary:

Slack	-1.938
Data Arrival Time	22.764
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_16_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/I1
9.683	1.026	tINS	FR	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/F
10.102	0.419	tNET	RR	2	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/I1
10.641	0.539	tINS	RF	3	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/SUM
12.105	1.464	tNET	FF	1	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/I1
12.927	0.822	tINS	FF	12	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/F
13.783	0.857	tNET	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/I1
14.882	1.099	tINS	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/F
16.188	1.305	tNET	FF	2	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/I0
17.233	1.045	tINS	FF	1	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/COUT
17.233	0.000	tNET	FF	2	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/CIN
17.290	0.057	tINS	FF	1	R7C23[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_13_s/COUT
17.290	0.000	tNET	FF	2	R7C23[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_14_s/CIN
17.853	0.563	tINS	FF	2	R7C23[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_14_s/SUM
19.164	1.311	tNET	FF	2	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/I0
20.209	1.045	tINS	FF	1	R9C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s/COUT
20.209	0.000	tNET	FF	2	R9C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s/CIN
20.737	0.528	tINS	FR	1	R9C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s/SUM
21.156	0.419	tNET	RR	2	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/I0
22.201	1.045	tINS	RF	1	R8C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_15_s0/COUT
22.201	0.000	tNET	FF	2	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_16_s0/CIN
22.764	0.563	tINS	FF	1	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_16_s0/SUM
22.764	0.000	tNET	FF	1	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_16_s0/CLK
20.826	-0.400	tSu		1	R8C25[1][A]	_DF2_FIR_CORE/_DATA_READ/rQL_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.279, 57.011%; route: 8.800, 40.861%; tC2Q: 0.458, 2.128%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path20

Path Summary:

Slack	-1.911
Data Arrival Time	22.737
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_14_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/I1
9.683	1.026	tINS	FR	1	R12C20[3][A]	_DF2_FIR_CORE/_DATA_READ/n264_s3/F
10.102	0.419	tNET	RR	2	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/I1
10.641	0.539	tINS	RF	3	R11C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n330_s/SUM
12.105	1.464	tNET	FF	1	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/I1
12.927	0.822	tINS	FF	12	R8C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s4/F
13.783	0.857	tNET	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/I1
14.882	1.099	tINS	FF	1	R7C20[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_12_s3/F
16.188	1.305	tNET	FF	2	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/I0
16.891	0.703	tINS	FF	2	R7C23[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_12_s/SUM
18.202	1.311	tNET	FF	2	R9C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s/I0
19.247	1.045	tINS	FF	1	R9C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_12_s/COUT
19.247	0.000	tNET	FF	2	R9C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s/CIN
19.810	0.563	tINS	FF	1	R9C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s/SUM
20.614	0.804	tNET	FF	2	R8C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s0/I1
21.164	0.550	tINS	FR	1	R8C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_13_s0/COUT
21.164	0.000	tNET	RR	2	R8C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s0/CIN
21.692	0.528	tINS	RR	1	R8C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_14_s0/SUM
22.111	0.419	tNET	RR	1	R7C25[0][B]	_DF2_FIR_CORE/_DATA_READ/n1434_s1/I2
22.737	0.626	tINS	RF	1	R7C25[0][B]	_DF2_FIR_CORE/_DATA_READ/n1434_s1/F
22.737	0.000	tNET	FF	1	R7C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_14_s0/CLK
20.826	-0.400	tSu		1	R7C25[0][B]	_DF2_FIR_CORE/_DATA_READ/rQL_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 11.448, 53.219%; route: 9.605, 44.650%; tC2Q: 0.458, 2.131%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path21

Path Summary:

Slack	-1.803
Data Arrival Time	22.629
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_19_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.351	0.814	tNET	FF	1	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.977	0.626	tINS	FF	4	R17C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.999	0.022	tNET	FF	1	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.625	0.626	tINS	FF	4	R17C19[1][A]	_DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.441	0.815	tNET	FF	1	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/I3
7.473	1.032	tINS	FF	9	R15C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.511	0.038	tNET	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.610	1.099	tINS	FF	1	R15C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n389_s3/F
9.414	0.804	tNET	FF	2	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.964	0.550	tINS	FR	1	R16C20[0][A]	_DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.964	0.000	tNET	RR	2	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/CIN
10.021	0.057	tINS	RF	1	R16C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n454_s/COUT
10.021	0.000	tNET	FF	2	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/CIN
10.584	0.563	tINS	FF	4	R16C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n453_s/SUM
11.895	1.311	tNET	FF	1	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I0
12.921	1.026	tINS	FR	3	R16C22[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
13.344	0.423	tNET	RR	1	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.970	0.626	tINS	RF	4	R15C22[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
14.803	0.832	tNET	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
15.902	1.099	tINS	FF	1	R14C23[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.907	0.005	tNET	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.939	1.032	tINS	FF	1	R14C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
18.228	1.289	tNET	FF	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
18.956	0.728	tINS	FR	2	R16C26[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/SUM
20.079	1.123	tNET	RR	2	R15C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s/I0
20.807	0.728	tINS	RR	1	R15C25[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s/SUM
21.928	1.121	tNET	RR	2	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s0/I1
22.629	0.701	tINS	RR	1	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_19_s0/SUM
22.629	0.000	tNET	RR	1	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_19_s0/CLK
20.826	-0.400	tSu		1	R14C24[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 11.525, 53.848%; route: 9.419, 44.011%; tC2Q: 0.458, 2.141%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path22

Path Summary:

Slack	-1.649
Data Arrival Time	22.474
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rQL_11_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
4.426	0.011	tNET	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/I1
5.458	1.032	tINS	FF	1	R12C19[3][A]	_DF2_FIR_CORE/_DATA_READ/n270_s3/F
6.262	0.804	tNET	FF	2	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/I1
6.812	0.550	tINS	FR	1	R11C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n336_s/COUT
6.812	0.000	tNET	RR	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/CIN
7.375	0.563	tINS	RF	2	R11C19[0][B]	_DF2_FIR_CORE/_DATA_READ/n335_s/SUM
9.005	1.630	tNET	FF	1	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/I2
9.827	0.822	tINS	FF	4	R9C19[1][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_6_s4/F
10.323	0.496	tNET	FF	1	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/I3
11.422	1.099	tINS	FF	4	R9C20[0][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s4/F
12.231	0.810	tNET	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/I1
13.330	1.099	tINS	FF	1	R8C21[2][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_9_s3/F
14.950	1.620	tNET	FF	2	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/I0
15.995	1.045	tINS	FF	1	R7C22[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_9_s/COUT
15.995	0.000	tNET	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/CIN
16.558	0.563	tINS	FF	2	R7C22[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUML_10_s/SUM
17.869	1.311	tNET	FF	2	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/I0
18.914	1.045	tINS	FF	1	R9C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUML_10_s/COUT
18.914	0.000	tNET	FF	2	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/CIN
19.442	0.528	tINS	FR	1	R9C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s/SUM
19.861	0.419	tNET	RR	2	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/I0
20.589	0.728	tINS	RR	1	R8C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUML_11_s0/SUM
21.375	0.786	tNET	RR	1	R8C27[0][A]	_DF2_FIR_CORE/_DATA_READ/n1431_s0/I0
22.474	1.099	tINS	RF	1	R8C27[0][A]	_DF2_FIR_CORE/_DATA_READ/n1431_s0/F
22.474	0.000	tNET	FF	1	R8C27[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C27[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_11_s0/CLK
20.826	-0.400	tSu		1	R8C27[0][A]	_DF2_FIR_CORE/_DATA_READ/rQL_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.056, 56.738%; route: 8.734, 41.105%; tC2Q: 0.458, 2.157%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path23

Path Summary:

Slack	-1.502
Data Arrival Time	22.328
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_14_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.037	0.500	tNET	FF	1	R17C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s3/I1
5.136	1.099	tINS	FF	1	R17C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s3/F
5.957	0.821	tNET	FF	2	R16C18[1][B]	_DF2_FIR_CORE/_DATA_READ/n464_s/I1
6.507	0.550	tINS	FR	1	R16C18[1][B]	_DF2_FIR_CORE/_DATA_READ/n464_s/COUT
6.507	0.000	tNET	RR	2	R16C18[2][A]	_DF2_FIR_CORE/_DATA_READ/n463_s/CIN
7.035	0.528	tINS	RR	2	R16C18[2][A]	_DF2_FIR_CORE/_DATA_READ/n463_s/SUM
7.458	0.423	tNET	RR	1	R16C19[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_3_s4/I3
8.280	0.822	tINS	RF	4	R16C19[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_3_s4/F
9.101	0.821	tNET	FF	1	R17C20[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_6_s4/I3
9.726	0.625	tINS	FR	4	R17C20[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_6_s4/F
10.157	0.431	tNET	RR	1	R17C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s4/I3
11.256	1.099	tINS	RF	4	R17C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s4/F
11.278	0.022	tNET	FF	1	R17C21[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s3/I1
12.310	1.032	tINS	FF	1	R17C21[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s3/F
13.933	1.624	tNET	FF	2	R16C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_9_s/I0
14.978	1.045	tINS	FF	1	R16C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_9_s/COUT
14.978	0.000	tNET	FF	2	R16C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_10_s/CIN
15.035	0.057	tINS	FF	1	R16C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_10_s/COUT
15.035	0.000	tNET	FF	2	R16C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_11_s/CIN
15.092	0.057	tINS	FF	1	R16C24[2][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_11_s/COUT
15.092	0.000	tNET	FF	2	R16C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_12_s/CIN
15.655	0.563	tINS	FF	2	R16C25[0][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_12_s/SUM
16.950	1.294	tNET	FF	2	R15C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_12_s/I0
17.995	1.045	tINS	FF	1	R15C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_12_s/COUT
17.995	0.000	tNET	FF	2	R15C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_13_s/CIN
18.558	0.563	tINS	FF	1	R15C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_13_s/SUM
19.362	0.804	tNET	FF	2	R14C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_13_s0/I1
19.912	0.550	tINS	FR	1	R14C23[2][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_13_s0/COUT
19.912	0.000	tNET	RR	2	R14C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_14_s0/CIN
20.475	0.563	tINS	RF	1	R14C24[0][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_14_s0/SUM
21.296	0.821	tNET	FF	1	R14C26[2][B]	_DF2_FIR_CORE/_DATA_READ/n1458_s1/I2
22.328	1.032	tINS	FF	1	R14C26[2][B]	_DF2_FIR_CORE/_DATA_READ/n1458_s1/F
22.328	0.000	tNET	FF	1	R14C26[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C26[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_14_s0/CLK
20.826	-0.400	tSu		1	R14C26[2][B]	_DF2_FIR_CORE/_DATA_READ/rQR_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.262, 58.108%; route: 8.382, 39.720%; tC2Q: 0.458, 2.172%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path24

Path Summary:

Slack	-1.176
Data Arrival Time	22.002
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0
To	_DF2_FIR_CORE/_DATA_READ/rSUML_19_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/CLK
1.684	0.458	tC2Q	RR	4	R12C20[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINL_7_s0/Q
2.107	0.423	tNET	RR	1	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/I2
3.168	1.061	tINS	RR	4	R12C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.593	0.425	tNET	RR	1	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.415	0.822	tINS	RF	4	R12C19[3][B]	_DF2_FIR_CORE/_DATA_READ/n270_s4/F
5.248	0.832	tNET	FF	1	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/I3
6.280	1.032	tINS	FF	4	R9C19[2][B]	_DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.302	0.022	tNET	FF	1	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/I3
7.334	1.032	tINS	FF	9	R9C19[0][A]	_DF2_FIR_CORE/_DATA_READ/n264_s4/F
8.657	1.324	tNET	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/I1
9.689	1.032	tINS	FF	1	R12C20[3][B]	_DF2_FIR_CORE/_DATA_READ/n263_s3/F
10.510	0.821	tNET	FF	2	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/I1
11.060	0.550	tINS	FR	1	R11C20[0][B]	_DF2_FIR_CORE/_DATA_READ/n329_s/COUT
11.060	0.000	tNET	RR	2	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/CIN
11.117	0.057	tINS	RF	1	R11C20[1][A]	_DF2_FIR_CORE/_DATA_READ/n328_s/COUT
11.117	0.000	tNET	FF	2	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/CIN
11.680	0.563	tINS	FF	3	R11C20[1][B]	_DF2_FIR_CORE/_DATA_READ/n327_s/SUM
12.490	0.810	tNET	FF	1	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
13.589	1.099	tINS	FF	3	R8C20[1][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
14.889	1.300	tNET	FF	1	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
15.915	1.026	tINS	FR	4	R11C22[2][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
16.337	0.423	tNET	RR	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
17.369	1.032	tINS	RF	1	R11C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
17.375	0.005	tNET	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
18.407	1.032	tINS	FF	1	R11C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
19.860	1.453	tNET	FF	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
20.588	0.728	tINS	FR	2	R7C24[0][B]	_DF2_FIR_CORE/_DATA_READ/wSUML_19_s/SUM
22.002	1.413	tNET	RR	1	R7C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_19_s0/CLK
20.826	-0.400	tSu		1	R7C25[2][A]	_DF2_FIR_CORE/_DATA_READ/rSUML_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 11.066, 53.263%; route: 9.252, 44.531%; tC2Q: 0.458, 2.206%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path25

Path Summary:

Slack	-1.066
Data Arrival Time	21.892
Data Required Time	20.826
From	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To	_DF2_FIR_CORE/_DATA_READ/rQR_18_s0
Launch Clk	iCLK:[R]
Latch Clk	iCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iCLK
0.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
0.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
1.226	0.244	tNET	RR	1	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.684	0.458	tC2Q	RF	5	R16C17[1][B]	_DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.505	0.821	tNET	FF	1	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.537	1.032	tINS	FF	4	R15C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s4/F
4.037	0.500	tNET	FF	1	R17C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s3/I1
5.136	1.099	tINS	FF	1	R17C18[3][B]	_DF2_FIR_CORE/_DATA_READ/n398_s3/F
5.957	0.821	tNET	FF	2	R16C18[1][B]	_DF2_FIR_CORE/_DATA_READ/n464_s/I1
6.507	0.550	tINS	FR	1	R16C18[1][B]	_DF2_FIR_CORE/_DATA_READ/n464_s/COUT
6.507	0.000	tNET	RR	2	R16C18[2][A]	_DF2_FIR_CORE/_DATA_READ/n463_s/CIN
7.035	0.528	tINS	RR	2	R16C18[2][A]	_DF2_FIR_CORE/_DATA_READ/n463_s/SUM
7.458	0.423	tNET	RR	1	R16C19[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_3_s4/I3
8.280	0.822	tINS	RF	4	R16C19[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_3_s4/F
9.101	0.821	tNET	FF	1	R17C20[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_6_s4/I3
9.726	0.625	tINS	FR	4	R17C20[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_6_s4/F
10.157	0.431	tNET	RR	1	R17C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s4/I3
11.256	1.099	tINS	RF	4	R17C21[3][B]	_DF2_FIR_CORE/_DATA_READ/wATTR_9_s4/F
11.278	0.022	tNET	FF	1	R17C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_12_s4/I3
12.310	1.032	tINS	FF	12	R17C21[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_12_s4/F
13.625	1.315	tNET	FF	1	R16C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_14_s3/I2
14.724	1.099	tINS	FF	1	R16C23[3][A]	_DF2_FIR_CORE/_DATA_READ/wATTR_14_s3/F
15.545	0.821	tNET	FF	2	R16C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_14_s/I0
16.590	1.045	tINS	FF	1	R16C25[1][A]	_DF2_FIR_CORE/_DATA_READ/wSUMR_14_s/COUT
16.590	0.000	tNET	FF	2	R16C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_15_s/CIN
17.153	0.563	tINS	FF	2	R16C25[1][B]	_DF2_FIR_CORE/_DATA_READ/wSUMR_15_s/SUM
18.293	1.141	tNET	FF	2	R15C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_15_s/I0
19.338	1.045	tINS	FF	1	R15C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_15_s/COUT
19.338	0.000	tNET	FF	2	R15C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_16_s/CIN
19.901	0.563	tINS	FF	1	R15C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_16_s/SUM
20.722	0.821	tNET	FF	2	R14C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_16_s0/I1
21.272	0.550	tINS	FR	1	R14C24[1][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_16_s0/COUT
21.272	0.000	tNET	RR	2	R14C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_17_s0/CIN
21.329	0.057	tINS	RF	1	R14C24[1][B]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_17_s0/COUT
21.329	0.000	tNET	FF	2	R14C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_18_s0/CIN
21.892	0.563	tINS	FF	1	R14C24[2][A]	_DF2_FIR_CORE/_DATA_READ/wQSUMR_18_s0/SUM
21.892	0.000	tNET	FF	1	R14C24[2][A]	_DF2_FIR_CORE/_DATA_READ/rQR_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iCLK
20.000	0.000	tCL	RR	1	IOL11[A]	iCLK_ibuf/I
20.982	0.982	tINS	RR	841	IOL11[A]	iCLK_ibuf/O
21.226	0.244	tNET	RR	1	R14C24[2][A]	_DF2_FIR_CORE/_DATA_READ/rQR_18_s0/CLK
20.826	-0.400	tSu		1	R14C24[2][A]	_DF2_FIR_CORE/_DATA_READ/rQR_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 12.272, 59.381%; route: 7.936, 38.401%; tC2Q: 0.458, 2.218%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.534
Data Arrival Time	11.176
Data Required Time	11.710
From	_DF2_FIR_CORE/_DF_CONTROL/n865_s0
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
10.452	0.452	tNET	FF	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/n865_s0/I2
11.176	0.724	tINS	FR	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/n865_s0/F
11.176	0.000	tNET	RR	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
11.680	1.680	tNET	FF	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/G
11.710	0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
11.710	0.000	tHld		1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1

Path Statistics:

Clock Skew	1.680
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 61.591%; route: 0.000, 0.000%; tC2Q: 0.452, 38.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.680, 100.000%

Path2

Path Summary:

Slack	-0.534
Data Arrival Time	11.176
Data Required Time	11.710
From	_DF2_FIR_CORE/_DF_CONTROL/n819_s0
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
10.452	0.452	tNET	FF	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/n819_s0/I3
11.176	0.724	tINS	FR	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/n819_s0/F
11.176	0.000	tNET	RR	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
11.680	1.680	tNET	FF	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/G
11.710	0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
11.710	0.000	tHld		1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1

Path Statistics:

Clock Skew	1.680
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 61.591%; route: 0.000, 0.000%; tC2Q: 0.452, 38.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.680, 100.000%

Path3

Path Summary:

Slack	-0.400
Data Arrival Time	1.969
Data Required Time	2.368
From	_SAI_INPUT/rSHH_15_s0
To	_SAI_INPUT/rDL_14_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C4[0][B]	_SAI_INPUT/rSHH_15_s0/CLK
1.362	0.333	tC2Q	RF	2	R12C4[0][B]	_SAI_INPUT/rSHH_15_s0/Q
1.969	0.606	tNET	FF	1	R12C5[0][A]	_SAI_INPUT/rDL_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.338	2.338	tNET	RR	1	R12C5[0][A]	_SAI_INPUT/rDL_14_s0/CLK
2.368	0.030	tUnc				_SAI_INPUT/rDL_14_s0
2.368	0.000	tHld		1	R12C5[0][A]	_SAI_INPUT/rDL_14_s0

Path Statistics:

Clock Skew	1.309
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.338, 100.000%

Path4

Path Summary:

Slack	-0.397
Data Arrival Time	1.966
Data Required Time	2.362
From	_SAI_INPUT/rSHL_10_s0
To	_SAI_INPUT/rDR_9_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C2[1][A]	_SAI_INPUT/rSHL_10_s0/CLK
1.362	0.333	tC2Q	RF	1	R16C2[1][A]	_SAI_INPUT/rSHL_10_s0/Q
1.966	0.603	tNET	FF	1	R17C2[1][B]	_SAI_INPUT/rDR_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R17C2[1][B]	_SAI_INPUT/rDR_9_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_9_s0
2.362	0.000	tHld		1	R17C2[1][B]	_SAI_INPUT/rDR_9_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path5

Path Summary:

Slack	-0.397
Data Arrival Time	1.966
Data Required Time	2.362
From	_SAI_INPUT/rSHH_26_s0
To	_SAI_INPUT/rDL_26_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R15C4[1][A]	_SAI_INPUT/rSHH_26_s0/CLK
1.362	0.333	tC2Q	RF	1	R15C4[1][A]	_SAI_INPUT/rSHH_26_s0/Q
1.966	0.603	tNET	FF	1	R15C5[2][B]	_SAI_INPUT/rDL_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R15C5[2][B]	_SAI_INPUT/rDL_26_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDL_26_s0
2.362	0.000	tHld		1	R15C5[2][B]	_SAI_INPUT/rDL_26_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path6

Path Summary:

Slack	-0.393
Data Arrival Time	1.969
Data Required Time	2.362
From	_SAI_INPUT/rSHL_19_s0
To	_SAI_INPUT/rDR_18_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C4[1][B]	_SAI_INPUT/rSHL_19_s0/CLK
1.362	0.333	tC2Q	RF	2	R16C4[1][B]	_SAI_INPUT/rSHL_19_s0/Q
1.969	0.606	tNET	FF	1	R17C4[0][A]	_SAI_INPUT/rDR_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R17C4[0][A]	_SAI_INPUT/rDR_18_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_18_s0
2.362	0.000	tHld		1	R17C4[0][A]	_SAI_INPUT/rDR_18_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path7

Path Summary:

Slack	-0.393
Data Arrival Time	1.969
Data Required Time	2.362
From	_SAI_INPUT/rSHL_24_s0
To	_SAI_INPUT/rDR_23_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R17C3[2][A]	_SAI_INPUT/rSHL_24_s0/CLK
1.362	0.333	tC2Q	RF	2	R17C3[2][A]	_SAI_INPUT/rSHL_24_s0/Q
1.969	0.606	tNET	FF	1	R17C4[2][B]	_SAI_INPUT/rDR_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R17C4[2][B]	_SAI_INPUT/rDR_23_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_23_s0
2.362	0.000	tHld		1	R17C4[2][B]	_SAI_INPUT/rDR_23_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path8

Path Summary:

Slack	-0.393
Data Arrival Time	1.969
Data Required Time	2.362
From	_SAI_INPUT/rSHH_24_s0
To	_SAI_INPUT/rDL_23_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R15C5[0][A]	_SAI_INPUT/rSHH_24_s0/CLK
1.362	0.333	tC2Q	RF	2	R15C5[0][A]	_SAI_INPUT/rSHH_24_s0/Q
1.969	0.606	tNET	FF	1	R15C5[1][B]	_SAI_INPUT/rDL_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R15C5[1][B]	_SAI_INPUT/rDL_23_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDL_23_s0
2.362	0.000	tHld		1	R15C5[1][B]	_SAI_INPUT/rDL_23_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path9

Path Summary:

Slack	-0.390
Data Arrival Time	1.966
Data Required Time	2.356
From	_SAI_INPUT/rSHL_26_s0
To	_SAI_INPUT/rDR_26_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R17C3[1][A]	_SAI_INPUT/rSHL_26_s0/CLK
1.362	0.333	tC2Q	RF	1	R17C3[1][A]	_SAI_INPUT/rSHL_26_s0/Q
1.966	0.603	tNET	FF	1	R17C3[0][B]	_SAI_INPUT/rDR_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R17C3[0][B]	_SAI_INPUT/rDR_26_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDR_26_s0
2.356	0.000	tHld		1	R17C3[0][B]	_SAI_INPUT/rDR_26_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path10

Path Summary:

Slack	-0.387
Data Arrival Time	1.969
Data Required Time	2.356
From	_SAI_INPUT/rSHL_6_s0
To	_SAI_INPUT/rDR_5_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R15C2[2][A]	_SAI_INPUT/rSHL_6_s0/CLK
1.362	0.333	tC2Q	RF	2	R15C2[2][A]	_SAI_INPUT/rSHL_6_s0/Q
1.969	0.606	tNET	FF	1	R16C2[2][B]	_SAI_INPUT/rDR_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R16C2[2][B]	_SAI_INPUT/rDR_5_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDR_5_s0
2.356	0.000	tHld		1	R16C2[2][B]	_SAI_INPUT/rDR_5_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path11

Path Summary:

Slack	-0.387
Data Arrival Time	1.969
Data Required Time	2.356
From	_SAI_INPUT/rSHH_6_s0
To	_SAI_INPUT/rDL_5_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C2[0][A]	_SAI_INPUT/rSHH_6_s0/CLK
1.362	0.333	tC2Q	RF	2	R13C2[0][A]	_SAI_INPUT/rSHH_6_s0/Q
1.969	0.606	tNET	FF	1	R13C2[1][A]	_SAI_INPUT/rDL_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R13C2[1][A]	_SAI_INPUT/rDL_5_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDL_5_s0
2.356	0.000	tHld		1	R13C2[1][A]	_SAI_INPUT/rDL_5_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path12

Path Summary:

Slack	-0.387
Data Arrival Time	1.969
Data Required Time	2.356
From	_SAI_INPUT/rSHH_22_s0
To	_SAI_INPUT/rDL_21_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C5[1][A]	_SAI_INPUT/rSHH_22_s0/CLK
1.362	0.333	tC2Q	RF	2	R13C5[1][A]	_SAI_INPUT/rSHH_22_s0/Q
1.969	0.606	tNET	FF	1	R13C6[2][B]	_SAI_INPUT/rDL_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R13C6[2][B]	_SAI_INPUT/rDL_21_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDL_21_s0
2.356	0.000	tHld		1	R13C6[2][B]	_SAI_INPUT/rDL_21_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.606, 64.532%; tC2Q: 0.333, 35.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path13

Path Summary:

Slack	-0.383
Data Arrival Time	1.973
Data Required Time	2.356
From	_SAI_INPUT/rSHH_18_s0
To	_SAI_INPUT/rDL_17_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C4[0][A]	_SAI_INPUT/rSHH_18_s0/CLK
1.362	0.333	tC2Q	RF	2	R13C4[0][A]	_SAI_INPUT/rSHH_18_s0/Q
1.973	0.610	tNET	FF	1	R13C5[0][B]	_SAI_INPUT/rDL_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R13C5[0][B]	_SAI_INPUT/rDL_17_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDL_17_s0
2.356	0.000	tHld		1	R13C5[0][B]	_SAI_INPUT/rDL_17_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.610, 64.675%; tC2Q: 0.333, 35.325%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path14

Path Summary:

Slack	-0.372
Data Arrival Time	1.990
Data Required Time	2.362
From	_SAI_INPUT/rSHH_23_s0
To	_SAI_INPUT/rDL_22_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R15C5[0][B]	_SAI_INPUT/rSHH_23_s0/CLK
1.362	0.333	tC2Q	RR	2	R15C5[0][B]	_SAI_INPUT/rSHH_23_s0/Q
1.990	0.628	tNET	RR	1	R15C5[1][A]	_SAI_INPUT/rDL_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R15C5[1][A]	_SAI_INPUT/rDL_22_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDL_22_s0
2.362	0.000	tHld		1	R15C5[1][A]	_SAI_INPUT/rDL_22_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.628, 65.312%; tC2Q: 0.333, 34.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path15

Path Summary:

Slack	-0.366
Data Arrival Time	1.990
Data Required Time	2.356
From	_SAI_INPUT/rSHL_25_s0
To	_SAI_INPUT/rDR_24_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R17C3[1][B]	_SAI_INPUT/rSHL_25_s0/CLK
1.362	0.333	tC2Q	RR	2	R17C3[1][B]	_SAI_INPUT/rSHL_25_s0/Q
1.990	0.628	tNET	RR	1	R17C3[0][A]	_SAI_INPUT/rDR_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R17C3[0][A]	_SAI_INPUT/rDR_24_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDR_24_s0
2.356	0.000	tHld		1	R17C3[0][A]	_SAI_INPUT/rDR_24_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.628, 65.312%; tC2Q: 0.333, 34.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path16

Path Summary:

Slack	-0.349
Data Arrival Time	2.013
Data Required Time	2.362
From	_SAI_INPUT/rSHL_8_s0
To	_SAI_INPUT/rDR_7_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C2[0][A]	_SAI_INPUT/rSHL_8_s0/CLK
1.362	0.333	tC2Q	RR	2	R16C2[0][A]	_SAI_INPUT/rSHL_8_s0/Q
2.013	0.651	tNET	RR	1	R17C2[0][B]	_SAI_INPUT/rDR_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R17C2[0][B]	_SAI_INPUT/rDR_7_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_7_s0
2.362	0.000	tHld		1	R17C2[0][B]	_SAI_INPUT/rDR_7_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.651, 66.140%; tC2Q: 0.333, 33.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path17

Path Summary:

Slack	-0.120
Data Arrival Time	2.249
Data Required Time	2.368
From	_SAI_INPUT/rSHH_13_s0
To	_SAI_INPUT/rDL_12_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C4[1][B]	_SAI_INPUT/rSHH_13_s0/CLK
1.362	0.333	tC2Q	RR	2	R12C4[1][B]	_SAI_INPUT/rSHH_13_s0/Q
2.249	0.886	tNET	RR	1	R12C5[1][A]	_SAI_INPUT/rDL_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.338	2.338	tNET	RR	1	R12C5[1][A]	_SAI_INPUT/rDL_12_s0/CLK
2.368	0.030	tUnc				_SAI_INPUT/rDL_12_s0
2.368	0.000	tHld		1	R12C5[1][A]	_SAI_INPUT/rDL_12_s0

Path Statistics:

Clock Skew	1.309
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.886, 72.670%; tC2Q: 0.333, 27.330%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.338, 100.000%

Path18

Path Summary:

Slack	-0.114
Data Arrival Time	2.249
Data Required Time	2.362
From	_SAI_INPUT/rSHL_23_s0
To	_SAI_INPUT/rDR_22_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R17C3[2][B]	_SAI_INPUT/rSHL_23_s0/CLK
1.362	0.333	tC2Q	RR	2	R17C3[2][B]	_SAI_INPUT/rSHL_23_s0/Q
2.249	0.886	tNET	RR	1	R17C4[2][A]	_SAI_INPUT/rDR_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R17C4[2][A]	_SAI_INPUT/rDR_22_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_22_s0
2.362	0.000	tHld		1	R17C4[2][A]	_SAI_INPUT/rDR_22_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.886, 72.670%; tC2Q: 0.333, 27.330%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path19

Path Summary:

Slack	-0.108
Data Arrival Time	2.247
Data Required Time	2.356
From	_SAI_INPUT/rSHH_10_s0
To	_SAI_INPUT/rDL_9_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C3[1][A]	_SAI_INPUT/rSHH_10_s0/CLK
1.362	0.333	tC2Q	RR	1	R13C3[1][A]	_SAI_INPUT/rSHH_10_s0/Q
2.247	0.885	tNET	RR	1	R15C3[2][A]	_SAI_INPUT/rDL_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R15C3[2][A]	_SAI_INPUT/rDL_9_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDL_9_s0
2.356	0.000	tHld		1	R15C3[2][A]	_SAI_INPUT/rDL_9_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.885, 72.643%; tC2Q: 0.333, 27.357%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path20

Path Summary:

Slack	-0.107
Data Arrival Time	2.249
Data Required Time	2.356
From	_SAI_INPUT/rSHL_5_s0
To	_SAI_INPUT/rDR_4_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R15C2[2][B]	_SAI_INPUT/rSHL_5_s0/CLK
1.362	0.333	tC2Q	RR	2	R15C2[2][B]	_SAI_INPUT/rSHL_5_s0/Q
2.249	0.886	tNET	RR	1	R16C2[2][A]	_SAI_INPUT/rDR_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R16C2[2][A]	_SAI_INPUT/rDR_4_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDR_4_s0
2.356	0.000	tHld		1	R16C2[2][A]	_SAI_INPUT/rDR_4_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.886, 72.670%; tC2Q: 0.333, 27.330%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path21

Path Summary:

Slack	-0.079
Data Arrival Time	2.277
Data Required Time	2.356
From	_SAI_INPUT/rSHH_11_s0
To	_SAI_INPUT/rDL_10_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C4[2][B]	_SAI_INPUT/rSHH_11_s0/CLK
1.362	0.333	tC2Q	RR	2	R12C4[2][B]	_SAI_INPUT/rSHH_11_s0/Q
2.277	0.915	tNET	RR	1	R12C8[2][A]	_SAI_INPUT/rDL_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R12C8[2][A]	_SAI_INPUT/rDL_10_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDL_10_s0
2.356	0.000	tHld		1	R12C8[2][A]	_SAI_INPUT/rDL_10_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.915, 73.295%; tC2Q: 0.333, 26.705%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path22

Path Summary:

Slack	-0.066
Data Arrival Time	2.296
Data Required Time	2.362
From	_SAI_INPUT/rSHL_15_s0
To	_SAI_INPUT/rDR_14_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C3[0][B]	_SAI_INPUT/rSHL_15_s0/CLK
1.362	0.333	tC2Q	RR	2	R16C3[0][B]	_SAI_INPUT/rSHL_15_s0/Q
2.296	0.934	tNET	RR	1	R16C12[2][B]	_SAI_INPUT/rDR_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R16C12[2][B]	_SAI_INPUT/rDR_14_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_14_s0
2.362	0.000	tHld		1	R16C12[2][B]	_SAI_INPUT/rDR_14_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.934, 73.697%; tC2Q: 0.333, 26.303%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path23

Path Summary:

Slack	-0.066
Data Arrival Time	2.296
Data Required Time	2.362
From	_SAI_INPUT/rSHL_17_s0
To	_SAI_INPUT/rDR_16_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C4[2][B]	_SAI_INPUT/rSHL_17_s0/CLK
1.362	0.333	tC2Q	RR	2	R16C4[2][B]	_SAI_INPUT/rSHL_17_s0/Q
2.296	0.934	tNET	RR	1	R16C12[0][A]	_SAI_INPUT/rDR_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.332	2.332	tNET	RR	1	R16C12[0][A]	_SAI_INPUT/rDR_16_s0/CLK
2.362	0.030	tUnc				_SAI_INPUT/rDR_16_s0
2.362	0.000	tHld		1	R16C12[0][A]	_SAI_INPUT/rDR_16_s0

Path Statistics:

Clock Skew	1.303
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.934, 73.697%; tC2Q: 0.333, 26.303%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.332, 100.000%

Path24

Path Summary:

Slack	-0.060
Data Arrival Time	2.296
Data Required Time	2.356
From	_SAI_INPUT/rSHL_22_s0
To	_SAI_INPUT/rDR_21_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R16C4[0][A]	_SAI_INPUT/rSHL_22_s0/CLK
1.362	0.333	tC2Q	RR	2	R16C4[0][A]	_SAI_INPUT/rSHL_22_s0/Q
2.296	0.934	tNET	RR	1	R16C14[2][A]	_SAI_INPUT/rDR_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.326	2.326	tNET	RR	1	R16C14[2][A]	_SAI_INPUT/rDR_21_s0/CLK
2.356	0.030	tUnc				_SAI_INPUT/rDR_21_s0
2.356	0.000	tHld		1	R16C14[2][A]	_SAI_INPUT/rDR_21_s0

Path Statistics:

Clock Skew	1.297
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.934, 73.697%; tC2Q: 0.333, 26.303%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.326, 100.000%

Path25

Path Summary:

Slack	-0.051
Data Arrival Time	2.318
Data Required Time	2.368
From	_SAI_INPUT/rSHH_4_s0
To	_SAI_INPUT/rDL_3_s0
Launch Clk	iSCK:[R]
Latch Clk	_SAI_INPUT/rLRC:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C4[1][A]	_SAI_INPUT/rSHH_4_s0/CLK
1.362	0.333	tC2Q	RR	2	R13C4[1][A]	_SAI_INPUT/rSHH_4_s0/Q
2.318	0.955	tNET	RR	1	R12C5[1][B]	_SAI_INPUT/rDL_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
2.338	2.338	tNET	RR	1	R12C5[1][B]	_SAI_INPUT/rDL_3_s0/CLK
2.368	0.030	tUnc				_SAI_INPUT/rDL_3_s0
2.368	0.000	tHld		1	R12C5[1][B]	_SAI_INPUT/rDL_3_s0

Path Statistics:

Clock Skew	1.309
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.955, 74.135%; tC2Q: 0.333, 25.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.338, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntH_0_s1
To	_SAI_INPUT/rCntH_0_s1
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntH_0_s1
21.152	-0.043	tSu		1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path2

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntL_0_s1
To	_SAI_INPUT/rCntL_0_s1
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntL_0_s1
21.152	-0.043	tSu		1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path3

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntL_4_s0
To	_SAI_INPUT/rCntL_4_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntL_4_s0
21.152	-0.043	tSu		1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path4

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntH_1_s0
To	_SAI_INPUT/rCntH_1_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntH_1_s0
21.152	-0.043	tSu		1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path5

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntH_2_s0
To	_SAI_INPUT/rCntH_2_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntH_2_s0
21.152	-0.043	tSu		1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path6

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntH_3_s0
To	_SAI_INPUT/rCntH_3_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntH_3_s0
21.152	-0.043	tSu		1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path7

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntH_4_s0
To	_SAI_INPUT/rCntH_4_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntH_4_s0
21.152	-0.043	tSu		1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path8

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntL_1_s0
To	_SAI_INPUT/rCntL_1_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntL_1_s0
21.152	-0.043	tSu		1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path9

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntL_2_s0
To	_SAI_INPUT/rCntL_2_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntL_2_s0
21.152	-0.043	tSu		1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path10

Path Summary:

Slack	8.207
Data Arrival Time	12.946
Data Required Time	21.152
From	_SAI_INPUT/rCntL_3_s0
To	_SAI_INPUT/rCntL_3_s0
Launch Clk	_SAI_INPUT/rLRC:[F]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
12.946	2.946	tNET	FF	1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					iSCK
20.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
20.982	0.982	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
21.226	0.244	tNET	RR	1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0/CLK
21.196	-0.030	tUnc				_SAI_INPUT/rCntL_3_s0
21.152	-0.043	tSu		1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0

Path Statistics:

Clock Skew	1.226
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.946, 100.000%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path11

Path Summary:

Slack	10.653
Data Arrival Time	1.639
Data Required Time	12.292
From	_DF2_FIR_CORE/_DF_CONTROL/n699_s21
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
Launch Clk	iDF_MODE_d[1]:[R]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iDF_MODE_d[1]
0.000	0.000	tCL	RR	26	IOB20[A]	iDF_MODE_1_ibuf/O
0.677	0.677	tNET	RR	1	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1
1.303	0.626	tINS	RF	2	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/F
1.639	0.336	tNET	FF	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
12.365	2.365	tNET	FF	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/G
12.335	-0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
12.292	-0.043	tSu		1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1

Path Statistics:

Clock Skew	2.365
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.626, 38.194%; route: 0.336, 20.518%; tC2Q: 0.677, 41.288%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.365, 100.000%

Path12

Path Summary:

Slack	10.653
Data Arrival Time	1.639
Data Required Time	12.292
From	_DF2_FIR_CORE/_DF_CONTROL/n699_s21
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
Launch Clk	iDF_MODE_d[1]:[R]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iDF_MODE_d[1]
0.000	0.000	tCL	RR	26	IOB20[A]	iDF_MODE_1_ibuf/O
0.677	0.677	tNET	RR	1	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1
1.303	0.626	tINS	RF	2	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/F
1.639	0.336	tNET	FF	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
12.365	2.365	tNET	FF	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/G
12.335	-0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
12.292	-0.043	tSu		1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1

Path Statistics:

Clock Skew	2.365
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.626, 38.194%; route: 0.336, 20.518%; tC2Q: 0.677, 41.288%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.365, 100.000%

Path13

Path Summary:

Slack	19.158
Data Arrival Time	11.061
Data Required Time	30.219
From	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	iDF_MODE_d[1]:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
11.061	1.061	tNET	FF	1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iDF_MODE_d[1]
30.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
30.262	0.262	tNET	FF	1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/G
30.219	-0.043	tSu		1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1

Path Statistics:

Clock Skew	0.262
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.061, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.262, 100.000%

Path14

Path Summary:

Slack	19.158
Data Arrival Time	11.061
Data Required Time	30.219
From	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	iDF_MODE_d[1]:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
11.061	1.061	tNET	FF	1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iDF_MODE_d[1]
30.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
30.262	0.262	tNET	FF	1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/G
30.219	-0.043	tSu		1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1

Path Statistics:

Clock Skew	0.262
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.061, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.262, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.652
Data Arrival Time	11.073
Data Required Time	11.725
From	_DF2_FIR_CORE/_DF_CONTROL/n699_s21
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
10.452	0.452	tNET	FF	1	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1
10.837	0.385	tINS	FR	2	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/F
11.073	0.237	tNET	RR	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
11.680	1.680	tNET	FF	1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1/G
11.710	0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1
11.725	0.015	tHld		1	R4C5[1][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_0_s1

Path Statistics:

Clock Skew	1.680
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 35.871%; route: 0.237, 22.063%; tC2Q: 0.452, 42.067%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.680, 100.000%

Path2

Path Summary:

Slack	-0.652
Data Arrival Time	11.073
Data Required Time	11.725
From	_DF2_FIR_CORE/_DF_CONTROL/n699_s21
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
Launch Clk	iDF_MODE_d[1]:[F]
Latch Clk	_DF2_FIR_CORE/_DF_CONTROL/n820_5:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iDF_MODE_d[1]
10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
10.452	0.452	tNET	FF	1	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/I1
10.837	0.385	tINS	FR	2	R4C5[2][B]	_DF2_FIR_CORE/_DF_CONTROL/n699_s21/F
11.073	0.237	tNET	RR	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					_DF2_FIR_CORE/_DF_CONTROL/n820_5
10.000	0.000	tCL	FF	2	R4C5[0][B]	_DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
11.680	1.680	tNET	FF	1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1/G
11.710	0.030	tUnc				_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1
11.725	0.015	tHld		1	R4C5[1][B]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_7_s1

Path Statistics:

Clock Skew	1.680
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 35.871%; route: 0.237, 22.063%; tC2Q: 0.452, 42.067%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.680, 100.000%

Path3

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntH_0_s1
To	_SAI_INPUT/rCntH_0_s1
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntH_0_s1
1.074	0.015	tHld		1	R13C2[2][A]	_SAI_INPUT/rCntH_0_s1

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path4

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntL_0_s1
To	_SAI_INPUT/rCntL_0_s1
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntL_0_s1
1.074	0.015	tHld		1	R13C3[0][A]	_SAI_INPUT/rCntL_0_s1

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path5

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntL_4_s0
To	_SAI_INPUT/rCntL_4_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntL_4_s0
1.074	0.015	tHld		1	R12C3[2][A]	_SAI_INPUT/rCntL_4_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path6

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntH_1_s0
To	_SAI_INPUT/rCntH_1_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntH_1_s0
1.074	0.015	tHld		1	R12C2[0][B]	_SAI_INPUT/rCntH_1_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path7

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntH_2_s0
To	_SAI_INPUT/rCntH_2_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntH_2_s0
1.074	0.015	tHld		1	R12C2[1][A]	_SAI_INPUT/rCntH_2_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path8

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntH_3_s0
To	_SAI_INPUT/rCntH_3_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntH_3_s0
1.074	0.015	tHld		1	R12C2[1][B]	_SAI_INPUT/rCntH_3_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path9

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntH_4_s0
To	_SAI_INPUT/rCntH_4_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntH_4_s0
1.074	0.015	tHld		1	R12C2[2][A]	_SAI_INPUT/rCntH_4_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path10

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntL_1_s0
To	_SAI_INPUT/rCntL_1_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntL_1_s0
1.074	0.015	tHld		1	R12C3[0][B]	_SAI_INPUT/rCntL_1_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path11

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntL_2_s0
To	_SAI_INPUT/rCntL_2_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntL_2_s0
1.074	0.015	tHld		1	R12C3[1][A]	_SAI_INPUT/rCntL_2_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path12

Path Summary:

Slack	0.753
Data Arrival Time	1.827
Data Required Time	1.074
From	_SAI_INPUT/rCntL_3_s0
To	_SAI_INPUT/rCntL_3_s0
Launch Clk	_SAI_INPUT/rLRC:[R]
Latch Clk	iSCK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					_SAI_INPUT/rLRC
0.000	0.000	tCL	RR	68	R17C6[1][B]	_SAI_INPUT/rLRC_s0/Q
1.827	1.827	tNET	RR	1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iSCK
0.000	0.000	tCL	RR	1	IOL9[A]	iSCK_ibuf/I
0.844	0.844	tINS	RR	65	IOL9[A]	iSCK_ibuf/O
1.029	0.185	tNET	RR	1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0/CLK
1.059	0.030	tUnc				_SAI_INPUT/rCntL_3_s0
1.074	0.015	tHld		1	R12C3[1][B]	_SAI_INPUT/rCntL_3_s0

Path Statistics:

Clock Skew	1.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.827, 100.000%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path13

Path Summary:

Slack	10.543
Data Arrival Time	0.754
Data Required Time	-9.790
From	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1
Launch Clk	iDF_MODE_d[1]:[R]
Latch Clk	iDF_MODE_d[1]:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iDF_MODE_d[1]
0.000	0.000	tCL	RR	26	IOB20[A]	iDF_MODE_1_ibuf/O
0.754	0.754	tNET	RR	1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iDF_MODE_d[1]
-10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
-9.805	0.195	tNET	FF	1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1/G
-9.790	0.015	tHld		1	R7C5[2][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Adr_7_s1

Path Statistics:

Clock Skew	0.195
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.754, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.195, 100.000%

Path14

Path Summary:

Slack	10.543
Data Arrival Time	0.754
Data Required Time	-9.790
From	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1
To	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1
Launch Clk	iDF_MODE_d[1]:[R]
Latch Clk	iDF_MODE_d[1]:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iDF_MODE_d[1]
0.000	0.000	tCL	RR	26	IOB20[A]	iDF_MODE_1_ibuf/O
0.754	0.754	tNET	RR	1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iDF_MODE_d[1]
-10.000	0.000	tCL	FF	26	IOB20[A]	iDF_MODE_1_ibuf/O
-9.805	0.195	tNET	FF	1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1/G
-9.790	0.015	tHld		1	R4C5[0][A]	_DF2_FIR_CORE/_DF_CONTROL/wStg1Len_2_s1

Path Statistics:

Clock Skew	0.195
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.754, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.195, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_14_s0/CLK

MPW2

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_12_s0/CLK

MPW3

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_3_s0/CLK

MPW4

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_1_s0/CLK

MPW5

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_0_s0/CLK

MPW6

MPW Summary:

Slack:	7.308
Actual Width:	8.558
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDL_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.781	3.781	tNET	FF	_SAI_INPUT/rDL_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.338	2.338	tNET	RR	_SAI_INPUT/rDL_8_s0/CLK

MPW7

MPW Summary:

Slack:	7.311
Actual Width:	8.561
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDR_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.771	3.771	tNET	FF	_SAI_INPUT/rDR_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.332	2.332	tNET	RR	_SAI_INPUT/rDR_0_s0/CLK

MPW8

MPW Summary:

Slack:	7.311
Actual Width:	8.561
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDR_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.771	3.771	tNET	FF	_SAI_INPUT/rDR_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.332	2.332	tNET	RR	_SAI_INPUT/rDR_16_s0/CLK

MPW9

MPW Summary:

Slack:	7.311
Actual Width:	8.561
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDR_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.771	3.771	tNET	FF	_SAI_INPUT/rDR_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.332	2.332	tNET	RR	_SAI_INPUT/rDR_8_s0/CLK

MPW10

MPW Summary:

Slack:	7.311
Actual Width:	8.561
Required Width:	1.250
Type:	Low Pulse Width
Clock:	_SAI_INPUT/rLRC
Objects:	_SAI_INPUT/rDR_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			_SAI_INPUT/rLRC
10.000	0.000	tCL	FF	_SAI_INPUT/rLRC_s0/Q
13.771	3.771	tNET	FF	_SAI_INPUT/rDR_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			_SAI_INPUT/rLRC
20.000	0.000	tCL	RR	_SAI_INPUT/rLRC_s0/Q
22.332	2.332	tNET	RR	_SAI_INPUT/rDR_7_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
841	iCLK_d	-5.552	0.262
167	rOSEna[2]	13.590	2.297
92	wOUT_RD	10.257	3.270
76	n1206_3	11.294	3.767
75	wWR	14.659	1.832
73	rStart[4]	13.562	2.483
72	rAcc_35_6	13.562	3.152
68	rLRC	5.484	3.781
65	iSCK_d	15.423	0.262
55	wRAM_MAC_MUX	11.915	3.613

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C8	88.89%
R9C14	88.89%
R11C8	86.11%
R11C14	84.72%
R17C18	84.72%
R9C9	84.72%
R13C14	84.72%
R11C9	83.33%
R11C15	83.33%
R18C22	83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command