PnR Messages

Report Title PnR Report
Design File D:\Projects\GOWIN\DF2\DF2\impl\gwsynthesis\DF2.vg
Physical Constraints File ---
Timing Constraints File ---
Version V1.9.8.09
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Sat Jan 20 17:56:34 2024
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.813s, Elapsed time = 0h 0m 0.804s Placement Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.136s Placement Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.451s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.094s, Elapsed time = 0h 0m 0.088s Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Routing: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Time and Memory Usage CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 223MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1425/4608 30%
    --LUT,ALU,ROM16 1425(921 LUT, 504 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 990/3756 26%
    --Logic Register as Latch 4/3456 1%
    --Logic Register as FF 979/3456 28%
    --I/O Register as Latch 0/300 0%
    --I/O Register as FF 7/300 2%
CLS 1011/2304 43%
I/O Port 30 -
I/O Buf 30 -
    --Input Buf 18 -
    --Output Buf 12 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 4 SDPB
 40%
DSP 7 MULTALU36X18
87%
PLL 0/2 0%
DCS 0/4 0%
DQCE 0/12 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/6 0%
DLLDLY 0/6 0%
DHCEN 0/12 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/33(0%)
bank 1 0/24(0%)
bank 2 19/38(50%)
bank 3 11/25(44%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 5/8(62%)
LW 3/8(37%)
GCLK_PIN 4/6(66%)
PLL 0/2(0%)
CLKDIV 0/6(0%)
DLLDLY 0/6(0%)

Global Clock Signals:

Signal Global Clock Location
iCLK_d PRIMARY LEFT RIGHT
iSPI_SCK_d PRIMARY LEFT
iSCK_d PRIMARY LEFT
iDF_MODE_d[1] PRIMARY LEFT
n820_5 PRIMARY LEFT
rLRC LW -
wOUT_RD LW -
rOSEna[2] LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
iCLK 25/3 N in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iSPI_SCK 56/2 N in IOB19[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iSPI_DAT 34/2 N in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iSPI_CS 4/3 N in IOL3[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iATT[0] 38/2 N in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iATT[1] 40/2 N in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iDF_MODE[0] 42/2 N in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iDF_MODE[1] 58/2 N in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iODRW[0] 67/2 N in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iODRW[1] 65/2 N in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iOVS_MAX[0] 7/3 N in IOL4[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iOVS_MAX[1] 9/3 N in IOL6[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iBYPASS 10/3 N in IOL6[B] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iOSCSEL 48/2 N in IOB12[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iLRC 57/2 N in IOB19[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
iSCK 11/3 N in IOL9[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iDAT 12/3 N in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
iMUTE 59/2 N in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
oOSC1EN 50/2 N out IOB14[A] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oOSC2EN 52/2 N out IOB16[A] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oINOVS[0] 27/3 N out IOL13[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
oINOVS[1] 61/2 N out IOB21[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oINOVS[2] 63/2 N out IOB22[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oCLIPP 51/2 N out IOB14[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oDL 47/2 N out IOB11[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oDR 49/2 N out IOB12[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
oBCK 23/3 N out IOL10[I] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
oWCK 26/3 N out IOL11[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
oDG 29/3 N out IOL15[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
oMCKO 54/2 N out IOB16[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
144/0 - in IOT2[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
143/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
142/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
141/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
140/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
139/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
138/0 - in IOT7[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
137/0 - in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
136/0 - in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
135/0 - in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
134/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
133/0 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
132/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
131/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
130/0 - in IOT16[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
129/0 - in IOT16[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
128/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
126/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
124/0 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
123/0 - in IOT22[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
122/0 - in IOT22[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
121/0 - in IOT24[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
120/0 - in IOT24[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
119/0 - in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
118/0 - in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
117/0 - in IOT30[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
116/0 - in IOT30[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
115/0 - in IOT33[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
114/0 - in IOT33[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
113/0 - in IOT35[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
112/0 - in IOT35[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
111/0 - in IOT37[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
110/0 - in IOT37[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
32/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
34/2 iSPI_DAT in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
38/2 iATT[0] in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
39/2 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
40/2 iATT[1] in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
41/2 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
42/2 iDF_MODE[0] in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
43/2 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
44/2 - in IOB10[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
45/2 - in IOB10[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
46/2 - in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
47/2 oDL out IOB11[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
48/2 iOSCSEL in IOB12[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
49/2 oDR out IOB12[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
50/2 oOSC1EN out IOB14[A] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
51/2 oCLIPP out IOB14[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
52/2 oOSC2EN out IOB16[A] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
54/2 oMCKO out IOB16[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
56/2 iSPI_SCK in IOB19[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
57/2 iLRC in IOB19[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
58/2 iDF_MODE[1] in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
59/2 iMUTE in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
60/2 - in IOB21[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
61/2 oINOVS[1] out IOB21[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
62/2 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
63/2 oINOVS[2] out IOB22[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
64/2 - in IOB24[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
65/2 iODRW[1] in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
66/2 - in IOB26[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
67/2 iODRW[0] in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
68/2 - in IOB28[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
69/2 - in IOB28[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
70/2 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
71/2 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
75/2 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
72/2 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
78/2 - in IOB36[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
76/2 - in IOB36[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
3/3 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
4/3 iSPI_CS in IOL3[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
6/3 - in IOL3[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
7/3 iOVS_MAX[0] in IOL4[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
8/3 - in IOL4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
9/3 iOVS_MAX[1] in IOL6[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
10/3 iBYPASS in IOL6[B] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
11/3 iSCK in IOL9[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
12/3 iDAT in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
13/3 - in IOL10[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
14/3 - in IOL10[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
15/3 - in IOL10[C] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
16/3 - in IOL10[D] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
18/3 - out IOL10[E] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
20/3 - in IOL10[F] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
21/3 - in IOL10[G] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
22/3 - in IOL10[H] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
23/3 oBCK out IOL10[I] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
24/3 - in IOL10[J] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
25/3 iCLK in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA OFF NA 1.8
26/3 oWCK out IOL11[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
27/3 oINOVS[0] out IOL13[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
28/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
29/3 oDG out IOL15[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
30/3 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
106/1 - in IOR3[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
104/1 - in IOR3[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
102/1 - in IOR4[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
101/1 - in IOR4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
100/1 - in IOR6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
99/1 - in IOR6[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
98/1 - in IOR9[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
97/1 - in IOR9[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
96/1 - in IOR10[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
95/1 - in IOR10[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
94/1 - in IOR10[C] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
93/1 - in IOR10[D] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
92/1 - in IOR10[E] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
90/1 - in IOR10[F] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
88/1 - in IOR10[G] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
87/1 - in IOR10[H] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
86/1 - in IOR10[I] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
85/1 - in IOR10[J] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
84/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
83/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
82/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
81/1 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
80/1 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA -
79/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA -