| Report Title |
Power Analysis Report |
| Design File |
D:\Projects\GOWIN\DF2\DF2\impl\gwsynthesis\DF2.vg |
| Physical Constraints File |
--- |
| Timing Constraints File |
--- |
| Version |
V1.9.8.09 |
| Part Number |
GW1N-LV4LQ144C6/I5 |
| Device |
GW1N-4 |
| Created Time |
Sat Jan 20 17:56:34 2024
|
| Legal Announcement |
Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
31.822 |
| Quiescent Power (mW) |
8.856 |
| Dynamic Power (mW) |
22.966 |
| Junction Temperature |
25.927 |
| Theta JA |
29.000 |
| Max Allowed Ambient Temperature |
84.073 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
17.940 |
2.079 |
24.022 |
| VCCX |
2.500 |
0.336 |
2.424 |
6.901 |
| VCCO18 |
1.800 |
0.332 |
0.167 |
0.899 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
0.638 |
NA |
6.267 |
| IO |
2.775
| 0.933
| 15.000
|
| BSRAM |
8.052
| NA |
NA |
| DSP |
12.428
| NA |
1.989
|
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| DF2 |
21.118 |
21.118(21.090) |
| DF2/_DF2_FIR_CORE/ |
21.036 |
21.036(21.036) |
| DF2/_DF2_FIR_CORE/_ADR_GEN/ |
0.112 |
0.112(0.000) |
| DF2/_DF2_FIR_CORE/_COEF_RAM/ |
3.804 |
3.804(0.000) |
| DF2/_DF2_FIR_CORE/_DATA_READ/ |
0.302 |
0.302(0.000) |
| DF2/_DF2_FIR_CORE/_DF_CONTROL/ |
0.034 |
0.034(0.000) |
| DF2/_DF2_FIR_CORE/_FIR_MAC_L/ |
6.268 |
6.268(0.000) |
| DF2/_DF2_FIR_CORE/_FIR_MAC_R/ |
6.266 |
6.266(0.000) |
| DF2/_DF2_FIR_CORE/_FIR_RAM/ |
4.250 |
4.250(0.000) |
| DF2/_SAI_INPUT/ |
0.018 |
0.018(0.000) |
| DF2/_SAI_OUTPUT/ |
0.036 |
0.036(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| iSPI_SCK |
50.000 |
1.919 |
| iCLK |
50.000 |
19.179 |
| iDF_MODE_d[1] |
50.000 |
0.004 |
| _SAI_INPUT/rLRC |
50.000 |
0.006 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| _DF2_FIR_CORE/_DF_CONTROL/n820_5 |
50.000 |
0.002 |
| iSCK |
50.000 |
0.014 |