Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Projects\GOWIN\DF2\DF2.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Sat Jan 20 17:55:47 2024
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DF2
Synthesis Process Running parser:
    CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.55s, Peak memory usage = 214.492MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.197s, Peak memory usage = 214.492MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 214.492MB
    Optimizing Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 214.492MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 214.492MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 214.492MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 214.492MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 214.492MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 214.492MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 214.492MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 214.492MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 214.492MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 214.492MB
Generate output files:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.258s, Peak memory usage = 214.492MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 214.492MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 30
I/O Buf 30
    IBUF 18
    OBUF 8
    TBUF 4
Register 918
    DFF 34
    DFFE 628
    DFFS 4
    DFFSE 30
    DFFR 90
    DFFRE 88
    DFFC 19
    DFFCE 21
    DLC 3
    DLP 1
LUT 834
    LUT2 185
    LUT3 340
    LUT4 309
ALU 466
    ALU 466
INV 19
    INV 19
DSP 7
    MULTALU36X18 7
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 1319(853 LUTs, 466 ALUs) / 4608 29%
Register 918 / 3756 24%
  --Register as Latch 4 / 3756 1%
  --Register as FF 914 / 3756 24%
BSRAM 4 / 10 40%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
iCLK Base 20.000 50.0 0.000 10.000 iCLK_ibuf/I
iSCK Base 20.000 50.0 0.000 10.000 iSCK_ibuf/I
iSPI_SCK Base 20.000 50.0 0.000 10.000 iSPI_SCK_ibuf/I
rLRC Base 20.000 50.0 0.000 10.000 _SAI_INPUT/rLRC_s0/Q
n820_5 Base 20.000 50.0 0.000 10.000 _DF2_FIR_CORE/_DF_CONTROL/n820_s1/F
iDF_MODE_d[1] Base 20.000 50.0 0.000 10.000 iDF_MODE_1_ibuf/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 iCLK 50.0(MHz) 45.8(MHz) 18 TOP
2 iSCK 50.0(MHz) 222.4(MHz) 3 TOP
3 iSPI_SCK 50.0(MHz) 124.8(MHz) 6 TOP
4 iDF_MODE_d[1] 50.0(MHz) 315.5(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.838
Data Arrival Time 22.783
Data Required Time 20.945
From _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To _DF2_FIR_CORE/_DATA_READ/rQR_23_s0
Launch Clk iCLK[R]
Latch Clk iCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 iCLK
0.000 0.000 tCL RR 1 iCLK_ibuf/I
0.982 0.982 tINS RR 769 iCLK_ibuf/O
1.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.803 0.458 tC2Q RF 5 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.283 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.382 1.099 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n398_s4/F
3.862 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.488 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.968 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.594 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.074 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s4/I3
6.700 0.626 tINS FF 9 _DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.180 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.279 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/F
8.759 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.804 1.045 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.804 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n454_s/CIN
9.861 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n454_s/COUT
9.861 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n453_s/CIN
9.918 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n453_s/COUT
9.918 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n452_s/CIN
10.481 0.563 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/n452_s/SUM
10.961 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I1
12.060 1.099 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
12.540 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.362 0.822 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
13.842 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
14.664 0.822 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.144 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.243 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
16.723 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
17.681 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
17.681 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
17.738 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/COUT
17.738 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_21_s/CIN
18.301 0.563 tINS FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_21_s/SUM
18.781 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/I0
19.739 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/COUT
19.739 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s/CIN
20.302 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s/SUM
20.782 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/I0
21.740 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/COUT
21.740 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_23_s0/CIN
22.303 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_23_s0/SUM
22.783 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/rQR_23_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 iCLK
20.000 0.000 tCL RR 1 iCLK_ibuf/I
20.982 0.982 tINS RR 769 iCLK_ibuf/O
21.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rQR_23_s0/CLK
20.945 -0.400 tSu 1 _DF2_FIR_CORE/_DATA_READ/rQR_23_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 14.260, 66.516%; route: 6.720, 31.346%; tC2Q: 0.458, 2.138%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack -1.838
Data Arrival Time 22.783
Data Required Time 20.945
From _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0
To _DF2_FIR_CORE/_DATA_READ/rQL_23_s0
Launch Clk iCLK[R]
Latch Clk iCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 iCLK
0.000 0.000 tCL RR 1 iCLK_ibuf/I
0.982 0.982 tINS RR 769 iCLK_ibuf/O
1.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0/CLK
1.803 0.458 tC2Q RF 5 _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0/Q
2.283 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n273_s4/I1
3.382 1.099 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.862 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.488 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n270_s4/F
4.968 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n267_s4/I3
5.594 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.074 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s4/I3
6.700 0.626 tINS FF 9 _DF2_FIR_CORE/_DATA_READ/n264_s4/F
7.180 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s3/I1
8.279 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s3/F
8.759 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n330_s/I1
9.804 1.045 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n330_s/COUT
9.804 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n329_s/CIN
9.861 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n329_s/COUT
9.861 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n328_s/CIN
9.918 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n328_s/COUT
9.918 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n327_s/CIN
10.481 0.563 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/n327_s/SUM
10.961 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
12.060 1.099 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
12.540 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
13.362 0.822 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
13.842 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
14.664 0.822 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
15.144 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
16.243 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
16.723 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
17.681 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
17.681 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
17.738 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUML_20_s/COUT
17.738 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_21_s/CIN
18.301 0.563 tINS FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_21_s/SUM
18.781 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/I0
19.739 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/COUT
19.739 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s/CIN
20.302 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s/SUM
20.782 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/I0
21.740 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/COUT
21.740 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_23_s0/CIN
22.303 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_23_s0/SUM
22.783 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/rQL_23_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 iCLK
20.000 0.000 tCL RR 1 iCLK_ibuf/I
20.982 0.982 tINS RR 769 iCLK_ibuf/O
21.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rQL_23_s0/CLK
20.945 -0.400 tSu 1 _DF2_FIR_CORE/_DATA_READ/rQL_23_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 14.260, 66.516%; route: 6.720, 31.346%; tC2Q: 0.458, 2.138%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack -1.781
Data Arrival Time 22.726
Data Required Time 20.945
From _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To _DF2_FIR_CORE/_DATA_READ/rQR_22_s0
Launch Clk iCLK[R]
Latch Clk iCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 iCLK
0.000 0.000 tCL RR 1 iCLK_ibuf/I
0.982 0.982 tINS RR 769 iCLK_ibuf/O
1.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.803 0.458 tC2Q RF 5 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.283 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.382 1.099 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n398_s4/F
3.862 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.488 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.968 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.594 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.074 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s4/I3
6.700 0.626 tINS FF 9 _DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.180 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.279 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/F
8.759 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.804 1.045 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.804 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n454_s/CIN
9.861 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n454_s/COUT
9.861 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n453_s/CIN
9.918 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n453_s/COUT
9.918 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n452_s/CIN
10.481 0.563 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/n452_s/SUM
10.961 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I1
12.060 1.099 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
12.540 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.362 0.822 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
13.842 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
14.664 0.822 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.144 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.243 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
16.723 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
17.681 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
17.681 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
18.244 0.563 tINS FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/SUM
18.724 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/I0
19.682 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/COUT
19.682 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/CIN
20.245 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/SUM
20.725 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/I0
21.683 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/COUT
21.683 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/CIN
22.246 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_22_s0/SUM
22.726 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/rQR_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 iCLK
20.000 0.000 tCL RR 1 iCLK_ibuf/I
20.982 0.982 tINS RR 769 iCLK_ibuf/O
21.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rQR_22_s0/CLK
20.945 -0.400 tSu 1 _DF2_FIR_CORE/_DATA_READ/rQR_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 14.203, 66.427%; route: 6.720, 31.429%; tC2Q: 0.458, 2.144%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack -1.781
Data Arrival Time 22.726
Data Required Time 20.945
From _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0
To _DF2_FIR_CORE/_DATA_READ/rQL_22_s0
Launch Clk iCLK[R]
Latch Clk iCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 iCLK
0.000 0.000 tCL RR 1 iCLK_ibuf/I
0.982 0.982 tINS RR 769 iCLK_ibuf/O
1.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0/CLK
1.803 0.458 tC2Q RF 5 _DF2_FIR_CORE/_DATA_READ/rDINL_5_s0/Q
2.283 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n273_s4/I1
3.382 1.099 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n273_s4/F
3.862 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n270_s4/I3
4.488 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n270_s4/F
4.968 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n267_s4/I3
5.594 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n267_s4/F
6.074 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s4/I3
6.700 0.626 tINS FF 9 _DF2_FIR_CORE/_DATA_READ/n264_s4/F
7.180 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s3/I1
8.279 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n264_s3/F
8.759 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n330_s/I1
9.804 1.045 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n330_s/COUT
9.804 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n329_s/CIN
9.861 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n329_s/COUT
9.861 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n328_s/CIN
9.918 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n328_s/COUT
9.918 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n327_s/CIN
10.481 0.563 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/n327_s/SUM
10.961 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/I1
12.060 1.099 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/wATTL_15_s4/F
12.540 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/I2
13.362 0.822 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/wATTL_17_s4/F
13.842 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/I2
14.664 0.822 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s4/F
15.144 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/I1
16.243 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTL_19_s3/F
16.723 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_19_s/I0
17.681 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUML_19_s/COUT
17.681 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_20_s/CIN
18.244 0.563 tINS FF 2 _DF2_FIR_CORE/_DATA_READ/wSUML_20_s/SUM
18.724 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/I0
19.682 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_20_s/COUT
19.682 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/CIN
20.245 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s/SUM
20.725 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/I0
21.683 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_21_s0/COUT
21.683 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/CIN
22.246 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUML_22_s0/SUM
22.726 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/rQL_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 iCLK
20.000 0.000 tCL RR 1 iCLK_ibuf/I
20.982 0.982 tINS RR 769 iCLK_ibuf/O
21.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rQL_22_s0/CLK
20.945 -0.400 tSu 1 _DF2_FIR_CORE/_DATA_READ/rQL_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 14.203, 66.427%; route: 6.720, 31.429%; tC2Q: 0.458, 2.144%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack -1.243
Data Arrival Time 22.188
Data Required Time 20.945
From _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0
To _DF2_FIR_CORE/_DATA_READ/rQR_21_s0
Launch Clk iCLK[R]
Latch Clk iCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 iCLK
0.000 0.000 tCL RR 1 iCLK_ibuf/I
0.982 0.982 tINS RR 769 iCLK_ibuf/O
1.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/CLK
1.803 0.458 tC2Q RF 5 _DF2_FIR_CORE/_DATA_READ/rDINR_5_s0/Q
2.283 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n398_s4/I1
3.382 1.099 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n398_s4/F
3.862 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n395_s4/I3
4.488 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n395_s4/F
4.968 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n392_s4/I3
5.594 0.626 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/n392_s4/F
6.074 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s4/I3
6.700 0.626 tINS FF 9 _DF2_FIR_CORE/_DATA_READ/n389_s4/F
7.180 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/I1
8.279 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n389_s3/F
8.759 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n455_s/I1
9.804 1.045 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n455_s/COUT
9.804 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n454_s/CIN
9.861 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n454_s/COUT
9.861 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n453_s/CIN
9.918 0.057 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/n453_s/COUT
9.918 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/n452_s/CIN
10.481 0.563 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/n452_s/SUM
10.961 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/I1
12.060 1.099 tINS FF 3 _DF2_FIR_CORE/_DATA_READ/wATTR_15_s4/F
12.540 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/I2
13.362 0.822 tINS FF 4 _DF2_FIR_CORE/_DATA_READ/wATTR_17_s4/F
13.842 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/I2
14.664 0.822 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s4/F
15.144 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/I1
16.243 1.099 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wATTR_19_s3/F
16.723 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/I0
17.681 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wSUMR_19_s/COUT
17.681 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/CIN
18.244 0.563 tINS FF 2 _DF2_FIR_CORE/_DATA_READ/wSUMR_20_s/SUM
18.724 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/I0
19.682 0.958 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_20_s/COUT
19.682 0.000 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/CIN
20.245 0.563 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s/SUM
20.725 0.480 tNET FF 2 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/I0
21.708 0.983 tINS FF 1 _DF2_FIR_CORE/_DATA_READ/wQSUMR_21_s0/SUM
22.188 0.480 tNET FF 1 _DF2_FIR_CORE/_DATA_READ/rQR_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 iCLK
20.000 0.000 tCL RR 1 iCLK_ibuf/I
20.982 0.982 tINS RR 769 iCLK_ibuf/O
21.345 0.363 tNET RR 1 _DF2_FIR_CORE/_DATA_READ/rQR_21_s0/CLK
20.945 -0.400 tSu 1 _DF2_FIR_CORE/_DATA_READ/rQR_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 13.665, 65.560%; route: 6.720, 32.241%; tC2Q: 0.458, 2.199%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%