| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| _pll |
2 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|spi_gen2 |
14 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|spi_gen1 |
14 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|spi_data_right |
55 |
8 |
0 |
8 |
2 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|spi_data_left |
55 |
8 |
0 |
8 |
2 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|__rom_stinit |
6 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|__rom_dg_hi |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_output|__rom_cnt_cont |
6 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_output |
78 |
20 |
0 |
20 |
12 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
| __fir|__mac_control|mac_right |
57 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__mac_control|mac_left |
57 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__mac_control |
83 |
0 |
0 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_rom|__coef_rom1 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_rom|__coef_rom0 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_rom |
12 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_ram|ram_left |
83 |
0 |
0 |
0 |
62 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_ram |
157 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_read|__NShape |
8 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_read |
69 |
3 |
0 |
3 |
58 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_write |
8 |
5 |
0 |
5 |
54 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_adr |
57 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__data_adr |
36 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__init_adr |
114 |
0 |
2 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_control|__rom_coef_control |
7 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__coef_control |
9 |
98 |
2 |
98 |
120 |
98 |
98 |
98 |
0 |
0 |
0 |
0 |
0 |
| __fir|__clk_control|__rom_st_last |
5 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir|__clk_control |
7 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __fir |
79 |
4 |
0 |
4 |
54 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| __sai_input|__att_4x12 |
37 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| __sai_input |
12 |
4 |
0 |
4 |
63 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |