# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 
# do DF1_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/defines.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/config.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/DF1.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll
# -- Compiling module att_4x12
# -- Compiling module SAI_input
# -- Compiling module rom_st_last
# -- Compiling module clk_control
# -- Compiling module rom_coef_control
# -- Compiling module coef_control
# -- Compiling module init_adr
# -- Compiling module data_adr
# -- Compiling module coef_adr
# -- Compiling module data_write
# -- Compiling module NoiseShape
# -- Compiling module data_read
# -- Compiling module ram_WxD
# -- Compiling module data_ram
# -- Compiling module Mac_Wx9_A
# -- Compiling module mac_control
# -- Compiling module coef_M4K_0
# -- Compiling module coef_M4K_1
# -- Compiling module coef_rom_9x1024
# -- Compiling module DF1_FIR_CORE
# -- Compiling module spi_data
# -- Compiling module spi_gen
# -- Compiling module rom_cnt_cont
# -- Compiling module rom_dg_hi
# -- Compiling module rom_stinit
# -- Compiling module SAI_output
# -- Compiling module DF1
# 
# Top level modules:
# 	DF1
# 
vsim +altera -do DF1_run_msim_rtl_verilog.do -l msim_transcript -gui cycloneii.cycloneii_pll(vital_pll)
# vsim +altera -do DF1_run_msim_rtl_verilog.do -l msim_transcript -gui cycloneii.cycloneii_pll(vital_pll) 
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading cycloneii.cycloneii_atom_pack(body)
# Loading cycloneii.cycloneii_pllpack(body)
# Loading cycloneii.cycloneii_pll(vital_pll)
# Loading cycloneii.cycloneii_m_cntr(behave)
# Loading cycloneii.cycloneii_n_cntr(behave)
# Loading cycloneii.cycloneii_scale_cntr(behave)
# do DF1_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/defines.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/config.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# vlog -vlog01compat -work work +incdir+C:/altera/13.0sp1/DF1_test {C:/altera/13.0sp1/DF1_test/DF1.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll
# -- Compiling module att_4x12
# -- Compiling module SAI_input
# -- Compiling module rom_st_last
# -- Compiling module clk_control
# -- Compiling module rom_coef_control
# -- Compiling module coef_control
# -- Compiling module init_adr
# -- Compiling module data_adr
# -- Compiling module coef_adr
# -- Compiling module data_write
# -- Compiling module NoiseShape
# -- Compiling module data_read
# -- Compiling module ram_WxD
# -- Compiling module data_ram
# -- Compiling module Mac_Wx9_A
# -- Compiling module mac_control
# -- Compiling module coef_M4K_0
# -- Compiling module coef_M4K_1
# -- Compiling module coef_rom_9x1024
# -- Compiling module DF1_FIR_CORE
# -- Compiling module spi_data
# -- Compiling module spi_gen
# -- Compiling module rom_cnt_cont
# -- Compiling module rom_dg_hi
# -- Compiling module rom_stinit
# -- Compiling module SAI_output
# -- Compiling module DF1
# 
# Top level modules:
# 	DF1
# 
