Код:
// Simple Series Audio Interface Output
module SSAI_OUTPUT
#( parameter
MCLKSEL = 0, // Master Clock Select: 0 - 1024Fs, 1 - 768Fs
// ********** Data Control **********************
DLEN = 24, // Output Data Length in bits
OB = 0, // 1 - offset binary, 0 - 2*s complement
DATINV = 0, // Output data invertion
// **********************************************
// ********** Bit Clock Control *****************
//BCKDIV = 3, // BCK = iCLK/(2^CKDIV)
BCKINV = 0, // 1 - invet BCK clokck: 0 = update data on falling BCK; 1 = update data on rising BCK
// **********************************************
// ********** Word Clock Control ****************
WCKW = 16, // WCK strobe width in iCLK periods
WCKINV = 0, // 1 - invet WCK strobe: 0 = update DAC on falling WCK; 1 = update DAC on rising WCK
// **********************************************
// ********** Deglitcher Control ****************
DGHW = 20, // 1..31 - deglitcher HOLD width
DGINV = 0 // 1 - invet DG strobe: 0 = 1-hold, 0-sample; 1 = 0-hold, 1-sample
// **********************************************
)
(
// input global signals
input iCLK, iCLRn,
// input control signals
input[2:0] iOVS_MAX,
input[2:0] iBCKDIV,
input iDGEN, // 1 - enable deglitcher signal
// input data
input [23:0] iDL, iDR,
// output data (LAT - not used)
output oDL, oDR, oBCK, oWCK, /*oLAT,*/ oDG
);
//**** Input Control Logic ****************
wire[2:0] wOvsMax = (iOVS_MAX > `OVS_MAX_x32) ? `OVS_MAX_x32 : iOVS_MAX;
wire signed[23:0] wCoding = OB << 23;
wire wDGCLR = (!iCLRn) ? 0 : iDGEN;
//*****************************************
//**** Control counter ********************
reg [9:0] rCNT;
wire[10:0] wMCKLIM = (MCLKSEL) ? 768 : 1024;
wire[9:0] wCntLim = (wMCKLIM >> wOvsMax) - 1;
wire wBCK = (iBCKDIV) ? rCNT[iBCKDIV-1] : !iCLK;
wire wLOAD = (rCNT == ((wCntLim - (DLEN << iBCKDIV)) & wCntLim)) ? 1 : 0;
//*****************************************
reg rBCK, rWCK, rDG;
reg[DLEN-1:0] rSHL, rSHR;
reg[14:0] wDGLIM;
wire[23:0] wDL = (DATINV) ? ~iDL : iDL;
wire[23:0] wDR = (DATINV) ? ~iDR : iDR;
//**** Output assigments *****************
assign oBCK = wBCK ^ BCKINV;
assign oWCK = rWCK ^ WCKINV;
assign oDG = rDG ^ DGINV;
assign oDL = rSHL[DLEN-1];
assign oDR = rSHR[DLEN-1];
//****************************************
//*****************************************
always@ * begin
case (wOvsMax)
`OVS_MAX_x1: wDGLIM = ((wMCKLIM>>`OVS_MAX_x1)-1) * DGHW;
`OVS_MAX_x2: wDGLIM = ((wMCKLIM>>`OVS_MAX_x2)-1) * DGHW;
`OVS_MAX_x4: wDGLIM = ((wMCKLIM>>`OVS_MAX_x4)-1) * DGHW;
`OVS_MAX_x8: wDGLIM = ((wMCKLIM>>`OVS_MAX_x8)-1) * DGHW;
`OVS_MAX_x16: wDGLIM = ((wMCKLIM>>`OVS_MAX_x16)-1) * DGHW;
`OVS_MAX_x32: wDGLIM = ((wMCKLIM>>`OVS_MAX_x32)-1) * DGHW;
default: wDGLIM = *hx;
endcase
end
//*****************************************
always@ (posedge iCLK or negedge iCLRn) begin
if (!iCLRn) begin
rCNT <= 0;
rBCK <= 0; rWCK <= 0;
rSHL <= 0; rSHR <= 0;
end
else begin
// Control timer to read address generate
rCNT <= (rCNT == wCntLim) ? 0 : (rCNT+1);
// Word Clock Processing Logic
if (rCNT == wCntLim) rWCK <= 0;
else if (rCNT == (wCntLim - WCKW)) rWCK <= 1;
// Load input data and shift to output
if (wLOAD) begin
rSHL <= (wDL >> (24-DLEN)) ^ wCoding;
rSHR <= (wDR >> (24-DLEN)) ^ wCoding;
end
else begin
if (iBCKDIV) begin
if (rCNT[iBCKDIV-1:0] == ((1<<iBCKDIV)-1)) begin
rSHL <= rSHL << 1;
rSHR <= rSHR << 1;
end
end
else begin
rSHL <= rSHL << 1;
rSHR <= rSHR << 1;
end
end
end
end
//**** Deglitcher signal processing ****************
always@ (posedge iCLK or negedge wDGCLR) begin
if (!wDGCLR) rDG <= 0;
else if (rCNT == wCntLim-1) rDG <= 1;
else if (rCNT == ((wDGLIM>>5)-1)) rDG <= 0;
end
endmodule
Ошибку выдает такую:
Код:
Error (10734): Verilog HDL error at SAI_OUTPUT.v(320): iBCKDIV is not a constant
Вот в этой строке:
Код:
if (rCNT[iBCKDIV-1:0] == ((1<<iBCKDIV)-1)) begin
DF2 - Вторая версия DIY ЦФ
Ответить с цитированием
Только дф2 пока могу. Верилог держит. 
Сообщение от Turbo_man
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